AD8002ARZ Analog Devices Inc, AD8002ARZ Datasheet - Page 14

• Manufacturer Part Number: AD8002ARZ
• Description: IC OPAMP CF DUAL LP LDIST 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8002ARZ

• Slew Rate: 1200 V/µs
• Amplifier Type: Current Feedback
• Number Of Circuits: 2
• -3db Bandwidth: 600MHz
• Current - Input Bias: 5µA
• Voltage - Input Offset: 2000µV
• Current - Supply: 10mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): ±3 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Current Feedback
• No. Of Amplifiers: 2
• Bandwidth: 600MHz
• Supply Voltage Range: ± 3V To ± 6V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8002
Layout Considerations
The specified high-speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper R
tion are mandatory.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure
13). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large tanta-
lum electrolytic capacitor (4.7 µF–10 µF) should be connected in
parallel, but not necessarily so close, to supply current for fast,
large-signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high-speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Component
R
R
R
R
R
R
Small Signal BW (MHz)
0.1 dB Flatness (MHz)
Component
R
R
R
R
R
R
Small Signal BW (MHz)
0.1 dB Flatness (MHz)
R
F
G
BT
C
S
T
F
G
BT
C
S
T
C
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
(Nominal) (Ω)
(Ω)
(Nominal) (Ω)
(Ω)
(Ω)
is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, R
(Nominal) (Ω)
(Nominal) (Ω)
F
design techniques and low parasitic component selec-
–10
499
49.9
49.9
49.9
–
–10
499
49.9
49.9
49.9
–
270
45
270
60
–2
549
274
49.9
49.9
61.9
380
80
–2
499
249
49.9
49.9
61.9
400
100
AD8002AN (DIP)
–1
576
576
49.9
49.9
54.9
410
130
AD8002ARM ( SOIC)
–1
590
590
49.9
49.9
49.9
410
100
Table I. Recommended Component Values
Gain
+1
1210
–
49.9
75
49.9
600
35
Gain
+1
1000
–
49.9
75
49.9
600
35
+2
750
750
49.9
75
49.9
500
60
+2
681
681
49.9
75
49.9
450
70
+10
499
54.9
49.9
0
49.9
170
24
+10
499
54.9
49.9
0
49.9
170
35
+100
1000
10
49.9
0
49.9
17
3
+100
1000
10
49.9
0
49.9
19
3
–10
499
49.9
49.9
49.9
–
250
50
IN
IN
+V
–V
S
S
Noninverting Configuration
Inverting Configuration
R
–2
499
249
49.9
49.9
61.9
410
100
T
R
R
Supply Bypassing
R
T
G
G
R
R
C
S
C
is not required.
C1
0.1 F
C2
0.1 F
AD8002AR (SOIC)
–1
549
549
49.9
49.9
54.9
410
100
–V
+V
–V
+V
R
R
S
F
S
S
F
S
Gain
+1
953
–
49.9
75
49.9
600
35
C3
10 F
C4
10 F
SEE TABLE I
R
R
BT
BT
+2
681
681
49.9
75
49.9
500
90
OUT
OUT
+10
499
54.9
49.9
0
49.9
170
24
10
3
+100
1000
49.9
0
49.9
17