AD8369ARUZ Analog Devices Inc, AD8369ARUZ Datasheet - Page 4

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AD8369ARUZ

Manufacturer Part Number
AD8369ARUZ
Description
IC AMP VGA 16TSSOP
Manufacturer
Analog Devices Inc
Series
X-AMP®r
Datasheet

Specifications of AD8369ARUZ

Amplifier Type
Variable Gain
Number Of Circuits
1
Slew Rate
1200 V/µs
-3db Bandwidth
600MHz
Current - Input Bias
160µA
Current - Supply
37mA
Voltage - Supply, Single/dual (±)
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
No. Of Amplifiers
1
Bandwidth
380MHz
Gain Accuracy
0.05dB
No. Of Channels
1
Supply Voltage Range
3V To 5.5V
Amplifier Case Style
TSSOP
No. Of Pins
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
Current - Output / Channel
-
Gain Bandwidth Product
-
Voltage - Input Offset
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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AD8369
SPECIFICATIONS
Parameter
Frequency = 380 MHz
Specifications subject to change without notice.
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(V
Parameter
Minimum Clock Pulsewidth (T
Minimum Clock Period (T
Minimum Setup Time Data vs. Clock (T
Minimum Setup Time Data Enable vs. Clock (T
Minimum Hold Time Clock vs. Data Enable (T
Minimum Hold Time Data vs. Clock (T
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(V
Parameter
Minimum Setup Time Data Enable vs. Data (T
Minimum Hold Time Data Enable vs. Data (T
Minimum Data Enable Width (T
DATA
(BIT 0)
CLOCK
(BIT 1)
DATA
ENABLE
(DENB)
S
S
= 5 V, T = 25
= 5 V, T = 25
Voltage Gain
Gain Flatness
Noise Figure
Output IP3
IMD
Harmonic Distortion
P1dB
CLOCK
DISABLED
3
C)
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
C)
T
ES
Serial Programming Timing
T
DS
MSB
T
(Continued)
DH
CK
)
PW
MSB–1
PW
)
)
ENABLED
Conditions
Within ± 20 MHz of 380 MHz
f1 = 379.55 MHz, f2 = 380.45 MHz
f1 = 379.55 MHz, f2 = 380.45 MHz,
V
Second-Order, V
Third-Order, V
For ± 1 dB deviation from linear gain
CLOCK
T
OPHI
PW
DH
DS
MSB–2
– V
)
)
OPLO
EH
T
ES
EH
CK
ES
)
)
)
)
= 1 V p-p composite
OPHI
LSB
OPHI
(NOT TO SCALE)
Typ
10
20
2
2
2
4
Typ
2
2
4
T
– V
EH
– V
OPLO
OPLO
CLOCK
DISABLED
–4–
= 1 V p-p
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
= 1 V p-p
Min
DATA IS LATCHED ON HIGH-TO-LOW
TRANSITION OF DENB
MSB
(BIT3)
MSB–1
(BIT2)
MSB–2
(BIT1)
LSB
(BIT0)
DENB
Parallel Programming Timing
T
ES
Typ
38.5
± 0.15
7.8
+8.5
+8.5
–47
–45
–49
+0.5
+0.5
T
EH
T
PW
Max
(NOT TO SCALE)
Unit
dB
dB
dB
dBV rms
dBm
dBc
dBc
dBc
dBV rms
dBm
REV. 0

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