MCP6271-E/P Microchip Technology, MCP6271-E/P Datasheet - Page 14

• Manufacturer Part Number: MCP6271-E/P
• Description: IC OPAMP 2.0V SNGL R-R 8DIP
• Manufacturer: Microchip Technology

Specifications of MCP6271-E/P

• Slew Rate: 0.9 V/µs
• Package / Case: 8-DIP (0.300", 7.62mm)
• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 170µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Number Of Channels: 1
• Common Mode Rejection Ratio (min): 70 dB
• Input Offset Voltage: 3 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Shutdown: No
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Technology: CMOS
• Voltage Gain Db: 110 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP6XXXDM-FLTR - KIT DEMO BOARD ACTIVE FILTER
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP6271/2/3/4/5
4.8.2
The non-inverting integrator shown in Figure 4-8 is easy
to build. It saves one op amp over the typical Miller
integrator plus inverting amplifier configuration. The
phase accuracy of this integrator depends on the
matching of the input and feedback resistors, and the
capacitor’s time constants. R
feedback at frequencies << 1/(2 R
a lossy integrator (it has infinite gain at DC).
FIGURE 4-8:
DS21810D-page 14
V
IN
R
LOSSY NON-INVERTING
INTEGRATOR
1
C
Non-Inverting Integrator.
R
1
2
+
MCP6271
_
F
R
1
is used to provide
C
1
R
C
C
1
F
2
1
=
) and makes this
R
2
R
F
V
C
OUT
2
4.8.3
The MCP6275 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery-powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
4.8.3.1
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions where op amp A is driving capacitive or low resis-
tive loads in the feedback loop (such as an integrator or
filter circuit) the op amp may not have sufficient source
current to drive the load. In this case, op amp B can be
used as a buffer.
FIGURE 4-9:
Buffer.
4.8.3.2
Figure 4-10 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this config-
uration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity-gain buffer).
Where:
V
V
V
OUT
OSA
OSB
G
G
A
B
=
CASCADED OP AMP
APPLICATIONS
A
= op amp A gain
= op amp B gain
= op amp A input offset voltage
= op amp B input offset voltage
Load Isolation
Cascaded Gain
V
IN
G
A
MCP6275
G
B
Isolating the Load with a
CS
+
 2004 Microchip Technology Inc.
V
OSA
G
A
G
B
B
+
V
OSB
Load
G
V
B
OUTB