MCP6G04-E/ST Microchip Technology, MCP6G04-E/ST Datasheet - Page 19

• Manufacturer Part Number: MCP6G04-E/ST
• Description: IC GAIN BLOCK 1.8V 4CH 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP6G04-E/ST

• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Slew Rate: 4.5 V/µs
• -3db Bandwidth: 900kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 110µA
• Current - Output / Channel: 20mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• No. Of Amplifiers: 4
• Bandwidth: 900kHz
• No. Of Channels: 1
• Supply Voltage Range: 1.8V To 5.5V
• Amplifier Case Style: TSSOP
• No. Of Pins: 14
• Operating Temperature Range: -40°C To +125°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Gain Bandwidth Product: -

4.0
The MCP6G01/1R/1U/2/3/4 family of Selectable Gain
Amplifiers (SGA) is based on simple analog building
blocks (see
explained in more detail in the following subsections.
FIGURE 4-1:
4.1
The internal op amp gives the right combination of
bandwidth, accuracy, and flexibility.
4.1.1
The internal op amp has three compensation
capacitors (comp. caps.) connected to a switching
network. They are selected to give good small signal
bandwidth at high gains, and good slew rate (full power
bandwidth) at low gains. The change in bandwidth as
gain changes is between 250 and 900 kHz. Refer to
Table 4-1
© 2006 Microchip Technology Inc.
GSEL
V
CS
Note:
IN
(V/V)
Gain
APPLICATIONS INFORMATION
Internal Op Amp
10
50
for more information.
1
Gain Select
COMPENSATION CAPACITORS
(MCP6G03
Figure
Switches
V
Logic
Gain
only)
5 MΩ
SS
is assumed to be 0V
4-1). Each of these blocks will be
V
0
V
DD
DD
SGA Block Diagram.
/2 (or open)
GSEL Voltage (Typ.)
V
V
SS
DD
3
(V)
R
R
G
F
V
OUT
MCP6G01/1R/1U/2/3/4
TABLE 4-1:
4.1.2
The input stage of the internal op amp uses two
differential input stages in parallel; one operates at low
V
With this topology, the internal inputs can operate to
0.3V past either supply rail, although the output will clip
the signal before that happens.
The inputs need to be kept within a smaller range to
prevent output clipping. The input offset voltage also
reduces the range; most designs will need the following
for normal operation:
EQUATION 4-1:
The transition between the two input stage occurs
when V
22). For the best distortion and gain linearity, avoid this
region of operation.
4.1.3
The
designed with CMOS input devices. It is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages.
exceeding both supplies with no resulting phase
inversion.
Note 1:
(V/V)
Gain
IN
10
50
1
(input voltage), while the other operates at high V
MCP6G01/1R/1U/2/3/4
2:
3:
4:
IN
Internal
Medium
Comp.
Large
Small
≈ V
Cap.
V
--------- -
Changing the compensation capacitor does not
change the DC performance (e.g., V
G x BW is approximately the Gain Bandwidth
Product of the internal op amp.
FPBW is the Full Power Bandwidth at
V
BW is the closed-loop, small signal –3 dB
bandwidth.
RAIL-TO-RAIL INPUTS
PHASE REVERSAL
G
OL
DD
DD
+
= 5.5V, which is based on slew rate (SR).
– 1.1V (see
V
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
G x BW
OS
(MHz)
Figure 2-7
Typ.
0.90
12.5
3.5
<
V
IN
<
Figure 2-19
(V/µs)
V
---------- - V
Typ.
0.50
SR
2.3
4.5
G
OH
shows an input voltage
amplifier
–
DS22004B-page 19
OS
FPBW
(kHz)
Typ.
133
260
29
and
OS
family
Figure 2-
).
(kHz)
Typ.
BW
900
350
250
IN
is
.