MCP6064-E/ST Microchip Technology, MCP6064-E/ST Datasheet - Page 15

• Manufacturer Part Number: MCP6064-E/ST
• Description: IC OPAMP PREC 6.0V 60UA 14-TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP6064-E/ST

• Slew Rate: 0.25 V/µs
• Package / Case: 14-TSSOP
• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 730kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 150µV
• Current - Supply: 60µA
• Current - Output / Channel: 27mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 4
• Common Mode Rejection Ratio (min): 72 dB
• Input Offset Voltage: 0.15 mV
• Input Bias Current (max): 100 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 6 V
• Supply Voltage (min): 1.8 V
• Technology: CMOS
• Voltage Gain Db: 115 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
The MCP6061/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high precision
applications.
4.1
4.1.1
The MCP6061/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages.
exceeding the supply voltage without any phase
reversal.
4.1.2
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see
Ratings
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors and to minimize input bias
current (I
FIGURE 4-1:
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V
clamp any voltages that go well above V
down voltage is high enough to allow normal operation,
but not low enough to protect against slow over-voltage
(beyond V
the spec) are limited so that damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
Figure 4-2
inputs.
© 2010 Microchip Technology Inc.
V
V
V
IN
DD
SS
+
†”).
APPLICATION INFORMATION
Rail-to-Rail Input
B
).
DD
Figure
Figure 2-34
Bond
Bond
Bond
shows one approach to protecting these
PHASE REVERSAL
INPUT VOLTAGE LIMITS
Pad
Pad
Pad
) events. Very fast ESD events (that meet
4-1. This structure was chosen to
Section 1.1 “Absolute Maximum
Simplified Analog Input ESD
Stage
Input
shows
the
Bond
Pad
DD
input
SS
; their break-
. They also
V
IN
voltage
–
FIGURE 4-2:
Inputs.
A significant amount of current can flow out of the
inputs when the Common Mode voltage (V
ground (V
4.1.3
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see
Ratings
Figure 4-3
inputs. The resistors R
rents in or out of the input pins (and the ESD diodes, D
and D
or V
FIGURE 4-3:
Inputs.
4.1.4
The input stage of the MCP6061/2/4 op amps use two
differential input stages in parallel. One operates at a
low common mode input voltage (V
operates at a high V
operates with a V
300 mV below V
voltage is measured at V
V
The transition between the input stages occurs when
V
Figure
gain linearity, with non-inverting gains, avoid this region
of operation.
DD
CM
V
V
V
V
SS
1
2
+ 0.3V to ensure proper operation.
1
2
is near V
2
.
). The diode currents will go through either V
2-6). For the best distortion performance and
†”).
SS
min(R
min(R
shows one approach to protecting these
INPUT CURRENT LIMITS
NORMAL OPERATION
). See
R
R
D
1
2
D
1
1
DD
1
1
SS
,R
,R
D
CM
Figure
. (See
– 1.1V (See
Section 1.1 “Absolute Maximum
2
2
D
2
MCP6061/2/4
CM
) >
) >
2
Protecting the Analog
Protecting the Analog
up to 300 mV above V
1
. With this topology, the device
max(V
V
and R
Figure
2-36.
SS
MCP606X
MCP606X
– min (V
CM
2 mA
2 mA
V
1
2
V
,V
DD
limit the possible cur-
2-13).The input offset
Figures
DD
U
2
= V
) – V
CM
U
1
DS22189B-page 15
1
1
), while the other
,V
SS
DD
2
2-4,
)
CM
– 0.3V and
) is below
V
V
2-5
OUT
DD
OUT
and
and
DD
1