MCP619T-I/ST Microchip Technology, MCP619T-I/ST Datasheet - Page 14
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MCP619T-I/ST
Manufacturer Part Number
MCP619T-I/ST
Description
IC OPAMP QUAD 2.3V R-R 14TSSOP
Manufacturer
Microchip Technology
Specifications of MCP619T-I/ST
Slew Rate
0.08 V/µs
Amplifier Type
General Purpose
Number Of Circuits
4
Output Type
Rail-to-Rail
Gain Bandwidth Product
190kHz
Current - Input Bias
15nA
Voltage - Input Offset
150µV
Current - Supply
19µA
Current - Output / Channel
17mA
Voltage - Supply, Single/dual (±)
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Op Amp Type
Precision
No. Of Amplifiers
1
Bandwidth
190kHz
Supply Voltage Range
2.3V To 5.5V
Amplifier Case Style
TSSOP
No. Of Pins
14
Number Of Channels
4
Voltage Gain Db
120 dB
Common Mode Rejection Ratio (min)
80 dB
Input Offset Voltage
0.15 mV
Operating Supply Voltage
3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
-3db Bandwidth
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP619T-I/ST
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP619T-I/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
MCP616/7/8/9
4.5
The MCP618 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typ.) and flows through the CS pin to V
this happens, the amplifier output is put into a high-
impedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier may
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.6
With this family of operational amplifiers, the power
supply pin (V
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It may use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
and can be shared with other analog parts.
4.7
An unused op amp in a quad package (MCP619)
should be configured as shown in Figure 4-6. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
FIGURE 4-6:
DS21613B-page 14
V
¼ MCP619 (A)
DD
MCP618 Chip Select (CS)
Supply Bypass
Unused Op Amps
DD
for single supply) should have a local
V
DD
Unused Op Amps.
¼ MCP619 (B)
V
DD
SS
. When
4.8
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA of current to flow, which is greater than the
MCP616/7/8/9 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example is shown below in Figure 4-7.
FIGURE 4-7:
for Inverting Gain.
1.
2.
Non-inverting Gain and Unity Gain Buffer:
a)
b)
Inverting Gain and Transimpedance gain (con-
vert current to voltage, such as photo detectors)
amplifiers:
a)
b)
PCB Surface Leakage
Connect the non-inverting pin (V
input with a wire that does not touch the
PCB surface.
Connect the guard ring to the inverting input
pin (V
common mode input voltage.
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the op
amp (e.g., V
Connect the inverting pin (V
with a wire that does not touch the PCB
surface.
Guard Ring
IN
–). This biases the guard ring to the
IN
DD
+). This biases the guard ring
Example Guard Ring Layout
© 2005 Microchip Technology Inc.
/2 or ground).
V
12
IN
– V
. A 5V difference would
IN
+
IN
–) to the input
V
SS
IN
+) to the