AD8012AR-REEL7 Analog Devices Inc, AD8012AR-REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD8012AR-REEL7
• Description: IC OPAMP CF DUAL LP 125MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8012AR-REEL7

• Rohs Status: RoHS non-compliant
• Amplifier Type: Current Feedback
• Number Of Circuits: 2
• Slew Rate: 2250 V/µs
• -3db Bandwidth: 350MHz
• Current - Input Bias: 3µA
• Voltage - Input Offset: 1500µV
• Current - Supply: 1.7mA
• Current - Output / Channel: 125mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Power Supply Requirement: Single/Dual
• Package Type: SOIC N
• Pin Count: 8
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIONS
Line Driving for HDSL
High bitrate digital subscriber line (HDSL) is becoming
popular as a means of providing full duplex data communication at
rates up to 1.544 MBPS or 2.048 MBPS over moderate distances
via conventional telephone twisted pair wires. Traditional T1
(E1 in Europe) requires repeaters every 3,000 feet to 6,000 feet
to boost the signal strength and allow transmission over distances
of up to 12,000 feet. In order to achieve repeaterless transmission
over this distance, an HDSL modem requires a transmitted
power level of 13.5 dBm (assuming a line impedance of 135 Ω).
HDSL uses the two binary/one quaternary line code (2B1Q).
A sample 2B1Q waveform is shown in Figure 5. The digital bit
stream is broken up into groups of two bits. Four analog volt-
ages (called quaternary symbols) are used to represent the four
possible combinations of two bits. These symbols are assigned
the arbitrary names +3, +1, –1, and –3. The corresponding
voltage levels are produced by a DAC that is usually part of an
analog front end circuit (AFEC). Before being applied to the
line, the DAC output is low-pass filtered and acquires the sinu-
soidal form shown in Figure 5. Finally, the filtered signal is
applied to the line driver. The line voltages that correspond to
the quaternary symbols +3, +1, –1, and –3 are 2.64 V, 0.88 V,
–0.88 V, and –2.64 V. This gives a peak-to-peak line voltage of
5.28 V.
Many of the elements of a classic differential line driver are
shown in the HDSL line driver in Figure 6. A 6 V peak-to-peak
differential signal is applied to the input. The differential gain of
the amplifier (1+2 R
tial output signal is 12 V p-p.
As is normal in telephony applications, a transformer galvani-
cally isolates the differential amplifier from the line. In this case,
a 1:1 turns ratio is used. In order to correctly terminate the line,
it is necessary to set the output impedance of the amplifier to be
equal to the impedance of the line being driven (135 Ω in this
case). Because the transformer has a turns ratio of 1:1, the
impedance reflected from the line is equal to the line impedance
of 135 Ω (R
resistors correctly terminate the line.
REV. B
Figure 5. Time Domain Representation of an HDSL Signal
SYMBOL
NAME
+3
+1
–3
–1
–2.64V
–0.88V
2.64V
0.88V
VOLTAGE
REFL
–1
01
= R
+3
10
F
LINE
+1
11
/R
G
DAC
OUTPUT
/Turns Ratio
) is set to +2, so the resulting differen-
FILTERED
OUTPUT
TO LINE
DRIVER
–3
00
–3
00
+1
11
2
+3
10
). As a result, two 66.5 Ω
–3
00
–1
01
–1
01
+1
11
–1
01
–3
00
–13–
The immediate effect of back-termination is that the signal from
the amplifier is halved before being applied to the line. This
doubles the power the amplifier must deliver. However, the
back-termination resistors also play an important second role.
Full-duplex data transmission systems like HDSL simulta-
neously transmit data in both directions. As a result, the signal
on the line and across the back termination resistors is the
composite of the transmitted and received signal. The termina-
tion resistors are used to tap off this signal and feed it to the
receive circuitry. Because the receive circuitry “knows” what is
being transmitted, the transmitted data can be subtracted from
the digitized composite signal to reveal the received data.
Driving a line with a differential signal offers a number of
advantages compared to a single-ended drive. Because the two
outputs are always 180 degrees out of phase relative to one
another, the differential signal output is double the output
amplitude of either of the op amps. As a result, the differential
amplifier can have a peak-to-peak swing of 16 V (each op amp
can swing to ± 4 V), even though the power supply is ± 5 V.
In addition, even-order harmonics (second, fourth, sixth, and
so on.) of the two single-ended outputs tend to cancel out one
another, so the total harmonic distortion (quadratic sum of all
harmonics) decreases compared to the single-ended case, even
as the signal amplitude is doubled. This is particularly advan-
tageous in the case of the second harmonic. Because it is very
close to the fundamental, filtering becomes difficult. In this
application, the THD is dominated by the third harmonic,
which is 65 dB below the carrier (i.e., spurious-free dynamic
range = –65 dBc).
Differential line driving also helps to preserve the integrity of the
transmitted signal in the presence of electromagnetic interfer-
ence (EMI). EMI tends to induce itself equally onto both the
positive and negative signal lines. As a result, a receiver with
good common-mode rejection will amplify the original signal
while rejecting induced (common-mode) EMI.
CIRCUITRY
CIRCUITRY
RECEIVER
RECEIVER
6V p-p
+
–
TO
TO
Figure 6. Differential for HDSL Applications
AD8012
AD8012
1.5k
R
G
1/2
1/2
+5V
–5V
750
750
R
R
0.1 F
0.1 F
F
F
12V p-p
66.5
66.5
1:1
GAIN = +2
6V p-p
12,000 FEET
UP TO
AD8012
1:1
135