AD711KR Analog Devices Inc, AD711KR Datasheet - Page 8

• Manufacturer Part Number: AD711KR
• Description: IC OPAMP BIFET PREC 25MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD711KR

• Rohs Status: RoHS non-compliant
• Amplifier Type: J-FET
• Number Of Circuits: 1
• Slew Rate: 20 V/µs
• -3db Bandwidth: 4MHz
• Current - Input Bias: 15pA
• Voltage - Input Offset: 200µV
• Current - Supply: 2.5mA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 9 V ~ 36 V, ±4.5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Output Type: -
• Gain Bandwidth Product: -

AD711
OP AMP SETTLING TIME—A MATHEMATICAL MODEL
The design of the AD711 gives careful attention to optimizing
individual circuit components; in addition, a careful tradeoff was
made: the gain bandwidth product (4 MHz) and slew rate
(20 V/ms) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD711
settles to ± 0.01%, with a 10 V output step, in under 1 ms, while
retaining the ability to drive a 100 pF load capacitance when
operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of w
the small signal behavior of the circuit of Figure 3a, consisting of
an op amp connected as an I-to-V converter at the output of a
bipolar or CMOS DAC. This equation would completely describe
the output of the system if not for the op amp’s finite slew rate
and other nonlinear effects.
where:
G
This equation may then be solved for C
In these equations, capacitor C
the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 3a
can be used directly; capacitance C
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
When R
equivalents, the general purpose inverting amplifier of Figure 26b
is created. Note that when using this general model, capacitance
C
w
2
N
X
p
o
Figure 3a. Simplified Model of the AD711 Used as a
Current-Out DAC Buffer
is either the input capacitance of the op amp if a simple inverting
= “noise” gain of circuit
=op amp’s unity gain frequency
I
O
C
V
I
IN
f
O
=
O
=
and I
2 - G
Rw
R
R(C
O
o
O
N
f
w
C
are replaced with their Thevenin V
= C
o
+
X
2 RC
X
)
s
o
AD711
2
/2p, Equation 1 will accurately describe
X
+
– R
w
Ê
Á
Ë
Rw
Ê
Á
Ë
o
G
1 +
w
+ (1 - G
X
N
o
o
is the total capacitor appearing
R
+ RC
R
C
O
X
R
F
ˆ
˜
¯
is the total capacitance of
N
f
f
)
ˆ
˜ s + 1
¯
:
R
L
C
IN
L
and R
V
OUT
IN
(3)
(3)
–8–
op amp is being simulated or it is the combined capacitance of
the DAC output and the op amp input if the DAC buffer is
being modeled.
In either case, the capacitance C
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of C
accuracy, Equation 2 can be used to choose a small capacitor,
C
Figure 4 is a graphical solution of Equation 2 for the AD711
with R = 4 kW.
The photos of Figures 5a and 5b show the dynamic response of
the AD711 in the settling test circuit of Figure 6.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
F
, to cancel the input pole and optimize amplifier response.
V
IN
Figure 3b. Simplified Model of the AD711
Used as an Inverter
Figure 4. Value of Capacitor C
60
50
40
30
20
10
0
R
0
IN
G
N
= 4.0
C
X
10
G
N
= 3.0
AD711
20
X
can be estimated with reasonable
G
X
N
30
C
= 2.0
causes the system to go from
F
C
R
F
G
N
F
40
= 1.0
vs. Value of C
R
L
G
50
N
= 1.5
C
L
60
X
REV. E
V
OUT