AD744KRZ Analog Devices Inc, AD744KRZ Datasheet - Page 11

• Manufacturer Part Number: AD744KRZ
• Description: IC OPAMP BIFET 13MHZ PREC 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD744KRZ

• Slew Rate: 75 V/µs
• Amplifier Type: J-FET
• Number Of Circuits: 1
• -3db Bandwidth: 13MHz
• Current - Input Bias: 30pA
• Voltage - Input Offset: 250µV
• Current - Supply: 3.5mA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Precision
• No. Of Amplifiers: 1
• Bandwidth: 13MHz
• Supply Voltage Range: ± 4.5V To ± 18V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Common Mode Rejection Ratio: 88
• Current, Input Bias: 30 pA
• Current, Input Offset: 10 pA
• Current, Output: 25 mA
• Harmonic Distortion: 0.0003 %
• Impedance, Thermal: 42 °C/W
• Package Type: SOIC-8
• Power Dissipation: 500 mW
• Resistance, Input: 3×10^12 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Input: ±20 V (Differential), -11.5 to +14.5 V (Common-Mode)
• Voltage, Noise: 45 nV/sqrt Hz
• Voltage, Offset: 0.25 mV
• Voltage, Output, High: +13.9 V
• Voltage, Output, Low: -13.3 V
• Voltage, Supply: ±15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Gain
Minimizing Settling Time in Real-World Applications
An amplifier with a “single pole” or “ideal” integrator open-loop
frequency response will achieve the minimum possible settling
time for any given unity-gain bandwidth. However, when this
“ideal” amplifier is used in a practical circuit, the actual settling
time is increased above the minimum value because of added
time constants which are introduced due to additional capacitance
on the amplifier’s summing junction. The following discussion
will explain how to minimize this increase in settling time by the
selection of the proper value for feedback capacitor, C
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency, f
small signal behavior of the circuit of Figure 39. This circuit
models an op amp connected as an I-to-V converter.
1
2
10
100
Table IV. Performance Summary for the 3 Op Amp
Instrumentation Amplifier Circuit
µ
NC
20 kΩ
2.22 kΩ
202 Ω
RG
O
, Equation 1 will accurately describe the
Bandwidth
3.5 MHz
2.5 MHz
1 MHz
290 kHz
T Settle (0.01%)
1.5 µs
1.0 µs
2 µs
5 µs
L
.
Equation 1 would completely describe the output of the system
if not for the op amp’s finite slew rate and other nonlinear
effects. Even considering these effects, the fine scale settling to
<0.1% will be determined by the op amp’s small signal behav-
ior. Equation 1.
Where F
This Equation May Then Be Solved for C
Equation 2.
In these equations, capacitance C
ing at the inverting terminal of the op amp. When modeling an
I-to-V converter application, the Norton equivalent circuit of
Figure 39 can be used directly. Capacitance C
tance of the output of the current source plus the input capacitance
of the op amp, which includes any stray capacitance at the op
amp’s input.
When R
equivalents, the general purpose inverting amplifier model of
Figure 40 is created. Here capacitor C
capacitance of the AD744 (5.5 pF) plus any stray capacitance
due to wiring and the type of IC package employed.
O
O
and I
= the op amp’s unity gain crossover frequency
V
V
I
G
IN
IN
C
I
O
O
N
L
=
O
= the “noise” gain of the circuit 1 +
=
R
R
IN
are replaced with their Thevenin V
R C
O
R 2πF
2 − G
(
2πF
C
L
X
C
N
AD744
X
+ C
O
O
AD744
C
+
COMP
C
X
2 RC
COMP
)
C
R
s
L
C
R
2
(OPTIONAL)
L
X
+
(OPTIONAL)
is the total capacitance appear-
– R



X
2πF
2πF
G
R 2πF
N
R
O
R
X
L
O
L
+ R C
represents the input
L
+ 1 − G
O
:



(
X
C
C
LOAD
is the total capaci-
LOAD
L

 s + 1

R
V
R
N
AD744
OUT
O
V
OUT
)



IN
and R
IN