MP39CL Cirrus Logic Inc, MP39CL Datasheet - Page 4

• Manufacturer Part Number: MP39CL
• Description: IC PWR OPAMP 100V 10A 30DIP
• Manufacturer: Cirrus Logic Inc
• Series: Apex Precision Power™r

Specifications of MP39CL

• Amplifier Type: Power
• Number Of Circuits: 1
• Slew Rate: 10 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 26mA
• Current - Output / Channel: 10A
• Voltage - Supply, Single/dual (±): 30 V ~ 100 V, ±15 V ~ 50 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 30-DIP Module
• Number Of Channels: 1
• Voltage Gain Db: 113 dB
• Common Mode Rejection Ratio (min): 86 dB
• Input Offset Voltage: 10 mV
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Maximum Dual Supply Voltage: +/- 50 V
• Minimum Operating Temperature: - 40 C
• For Use With: 598-1471 - EVAL KIT FOR MP38CL/MP39CL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1414; MP39CL

ABSOLUTE MAXIMUM RATINGS
SPECIFICATIONS
GENERAL
siderations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specification
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit; heat sink selection;
Apex’s complete Application Notes library; Technical Seminar
Workbook; and Evaluation Kits.
CURRENT LIMIT
across the current limit sense resistor. For the current limit
to work correctly pin 24 must be connected to the amplifier
output side and pin 23 connected to the load side of the current
limit resistor, R
bypass any parasitic resistances, Rp, formed by sockets and
solder joints as well as internal amplifier losses. The current
limiting resistor may not be placed anywhere in the output
circuit except where shown in Figure 1.
follows:
BOOST OPERATION
are operated at higher supply voltages than the amplifier's high
current output stage. +V
are connected to the high current output stage. An additional
10V on the V
to drive the output transistors into saturation and improve the
output voltage swing for extra efficient operation when required.
When close swing to the supply rails is not required the +V
and +V
and –V
lower than the V
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4
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.
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Please read Application Note 1 "General Operating Con-
The two current limit sense lines are to be connected directly
The value of the current limit resistor can be calculated as
With the V
S
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S
pins. The boost voltage pins must not be at a voltage
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pins must be strapped together as well as the –V
B
B
pins is sufficient to allow the small signal stages
feature the small signal stages of the amplifier
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S
, as shown in Figure 1. This connection will
pins.
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S
(pins 12-14) and –V
R
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LIMIT
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MP39U REV G JANUARY 2005 © 2005 Apex Microtechnology Corp .
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S
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(pins 18-20)
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B
B
BYPASSING
operation. Bypass the ±Vs pins with a aluminum electrolytic
capacitor with a value of at least 10µF per amp of expected
output current. In addition a .47µF to 1µF ceramic capacitor
should be placed in parallel with each aluminum electrolytic
capacitor. Both of these capacitors have to be placed as close
to the power supply pins as physically possible. If not connected
to the Vs pins (See BOOST OPERATION) the V
also be bypassed with a .47µF to 1µF ceramic capacitor.
USING THE IQ PIN FUNCTION
AB biasing current from the output stage. Typically this would
remove 1-4 mA of quiescent current. The resulting decrease
in quiescent power dissipation may be important in some
applications. Note that implementing this option will raise the
output impedance of the amplifier and increase crossover
distortion as well.
COMPENSATION
nected to pins 4 and 6. Unity gain stability can be achieved at
any compensation capacitance greater than 470 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate.
APPLICATION REFERENCES
lowing application notes.
AN 1
AN 11
AN 38
Proper bypassing of the power supply pins is crucial for proper
Pin 25 (Iq) can be tied to pin 6 (Cc1) to eliminate the class
The external compensation components C
For additional technical information please refer to the fol-
General Operating Considerations
Thermal Techniques
Loop Stability with Reactive Loads
MP39 • MP39A
C
and R
B
pins should
C
are con-