AD8632AR-REEL7 Analog Devices Inc, AD8632AR-REEL7 Datasheet - Page 9

• Manufacturer Part Number: AD8632AR-REEL7
• Description: IC OPAMP GP R-R 5MHZ DUAL 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8632AR-REEL7

• Rohs Status: RoHS non-compliant
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 3 V/µs
• Gain Bandwidth Product: 5MHz
• Current - Input Bias: 250nA
• Voltage - Input Offset: 800µV
• Current - Supply: 300µA
• Current - Output / Channel: 10mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• -3db Bandwidth: -

Battery
Lead-Acid
Lithium
NiMH
NiCd
Carbon-Zinc
RAIL-TO-RAIL INPUT AND OUTPUT
The AD8631 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier’s
supply set to 1.8 V, the input can be set to 1.8 V p-p, allowing the
output to swing to both rails without clipping. Figure 20 shows a
scope picture of both input and output taken at unity gain, with a
frequency of 1 kHz, at V
REV. 0
V
D1
D2
OUT
V
IN
IN
Table I. Typical Battery Life Voltage Range
Figure 20. Rail-to-Rail Input Output
V
V
ESD
ESD
R1
S
IN
= 1.8V
= 1.8V p-p
R9
Q3
R3
R7
R5
Nominal
Voltage (V)
2
2.6–3.6
1.2
1.2
1.5
S
Q1
= 1.8 V and V
D7
D8
TIME – 200 s/Div
Q2
I1
I2
R6
R8
R4
Q4
R10
ESD
ESD
IN
R2
D3
D4
= 1.8 V p-p.
End-of-Voltage
Discharge (V)
1.8
1.7–2.4
1
1
1.1
IN
C1
Figure 19. Simplified Schematic
Q8
Q5
Q10
V
I3
EE
I4
Q11
V
CC
–9–
Q9
Q6
The rail-to-rail feature of the AD8631 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.
INPUT BIAS CONSIDERATION
The input bias current (I
affects all op amps. I
voltage. This offset voltage is created by I
the negative feedback resistor R
R
(V
Obviously the lower the R
Using a compensation resistor, R
minimize this effect. With the input bias current minimized we
still need to be aware of the input offset current (I
generate a slight offset error. Figure 21 shows three different
configurations to minimize I
I5
F
OS
is 100 kΩ, the corresponding generated offset voltage is 25 mV
Q7
= I
R
Q13
B
= R
B
I7
Figure 21. Input Bias Cancellation Circuits
V
I
I
R
V
V
F
R
I
I
I6
F
).
R
B
Q14
R
R
I
I
= R
R
B
S
I
R11
can generate a somewhat significant offset
R
C2
F
I8
B
) is a non-ideal, real-life parameter that
F
the lower the generated voltage offset.
AD8631
AD8631
AD8631
Q15
B
R12
-induced offset errors.
R
F
R
. If I
F
F
R
C3
= R
B
F
, as shown in Figure 21, can
R13
AD8631/AD8632
D16
R14
S
B
Q19
is 250 nA (worst case), and
INVERTING CONFIGURATION
NONINVERTING CONFIGURATION
UNITY GAIN BUFFER
Q17
B
when flowing through
C4
V
OUT
Q20
Q18
V
V
OUT
OUT
OS
) which will
D9
D6
V
V
V
CC
OUT
EE