CLC520AJE National Semiconductor, CLC520AJE Datasheet - Page 10

• Manufacturer Part Number: CLC520AJE
• Description: IC AMP CTRL GAIN/AGC 14-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC520AJE

• Amplifier Type: Current Feedback
• Number Of Circuits: 1
• Slew Rate: 2000 V/µs
• -3db Bandwidth: 160MHz
• Current - Input Bias: 12µA
• Current - Supply: 28mA
• Current - Output / Channel: 60mA
• Voltage - Supply, Single/dual (±): 10 V ~ 14 V, ±5 V ~ 7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Other names: *CLC520AJE

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Application Information
the input signal, signal-to-noise ratio is maximized. The
maximum allowed input amplitude and from system specifi-
cations, using maximum required gain R
calculated.
The output stage op amp is a current-feedback type amplifier
optimized for R
To determine whether the maximum input amplitude will
overdrive the CLC520, compute:
the maximum differential input voltage for linear operation. If
the maximum input amplitude exceeds the above V
then CLC520 should either be moved to a location in the
signal chain where input amplitudes are reduced, or the
CLC520 gain A
and R
impact is different based on the choice made.
If the input amplitude is reduced, recompute the impact on
signal-to-noise ratio. If A
Post CLC520 amplifier gain, should be increased, or another
gain stage added to make up for reduced system gain..
To increase R
largest expected peak differential input voltage. Compute the
lowest acceptable value for R
Operating with R
eration of the input buffers.
R
R
R
reducing resistor to ground on the inverting summing node of
the output amplifier (see application note QA-13 for details).
Printed Circuit Layout
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive
Inverting-input (pin12); keep node trace area small. Shunt
f
f
f
R
should be
may be computed from selected R
<
g
1k can be implemented if necessary using a loop gain
>
f
V
should be increased. The overall system performance
740 ˚ V
dmax
to
FIGURE 4. CLC520 Noise Model
>
= (R
g
dmax
VMAX
f
= 1k for overall best performance, however
stray
= 1k . R
and R
g
g
+3.0 ) · 0.00135
larger than this value insures linear op-
−3
should be reduced or the values for R
f
capacitance
, where V
VMAX
g
can then be computed as:
g
is reduced,
:
dmax
g
to
and A
= (+V
(Continued)
f
ground
and R
VMAX
IN
)−(−V
dmax
:
g
at
can be
IN
) the
limit,
01275647
the
g
10
capacitance across the feedback resistor should not be used
to compensate for this effect.
For best performance at low maximum gains (A
R
ion. Capacitance to ground should be minimized by remov-
ing the ground plane from under the resistor of R
Parasitic or load capacitance directly on the output (pin 10)
degrades phase margin leading to frequency response
peaking. A small series resistor before this capacitance,
effectively reduces this effect (see Settling Time vs. Capaci-
tive Load).
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) must be used for R
mance. Precision buffed resistors are suggested for R
low gain settings (A
tors and RN55D metal-film resistors may be used with re-
duced performance.
Evaluation PC boards (part no. 730021) for the CLC520 are
available.
Predicting the output noise
Seven noise sources (e
model the CLC520 noise performance ( Figure 4 ). e
i
while i
buffer. To simplify the model e
R
R
included in i
An additional term E
contribution from the Gilbert multiplier core. Core noise is
theoretically zero when the multiplier is set to maximum gain
or zero gain (V
temperature) and reaches a maximum of 37nV/
A
Several points should be made concerning this model. First,
external component noise contributions need to be factored
in when computing total output referred noise. The only
exception is R
tored in. Second, the model ignores flicker noise contribu-
tions. Applications where noise below approximately 100kHz
must be considered should use this model with caution.
Third, this model very accurately predicts output noise volt-
age for the typical application circuit (see above) but accu-
racy will degrade the component values deviate further from
those in the typical application circuit. In general, however,
i
FIGURE 5. Equivalent Input Noise Voltage (e
VMAX
g
model the equivalent input noise terms for the input buffer
g
bias
+ and R
(see Figure 5 for e
is assumed noiseless and its noise contribution is
/2.
io
, i
no
g
, and e
io
connections should be treated in a similar fash-
.
g
, where its noise contribution is already fac-
g
>
1.6V or V
no
VMAX
n
model the noise terms for the output
core
vs. R
n
, i
n
<
mimics the active device noise
, i
10). Carbon composition resis-
g
g
i
). To simplify the model further,
, i
n
<
io
includes the effect of resistor
0.63V respectively at room
, i
no
, e
no
, E
f
for rated perfor-
core
01275648
) are used to
n
g
VMAX
) vs. R
.
n
, i
n
<
, and
g
10)
for
g
at