LF357N National Semiconductor, LF357N Datasheet - Page 12

• Manufacturer Part Number: LF357N
• Description: IC OP AMP JFET INPUT 8DIP
• Manufacturer: National Semiconductor
• Series: BI-FET™r

Specifications of LF357N

• Amplifier Type: J-FET
• Number Of Circuits: 1
• Slew Rate: 50 V/µs
• Gain Bandwidth Product: 20MHz
• Current - Input Bias: 30pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 5mA
• Voltage - Supply, Single/dual (±): 10 V ~ 36 V, ±5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -
• Other names: *LF357N; LF357

Typical Applications
f
R1 R4 matched Linearity 0 1% over 2 decades
e
Power BW f
Parasitic input capacitance C1 j (3 pF for LF155 LF156 and LF157 plus
any additional layout capacitance) interacts with feedback elements and
creates undesirable high frequency pole To compensate add C2 such
that R2 C2 j R1 C1
I
No additional phase shift added by the current amplifier
OUT(MAX)
V
(8 V
OUT
T
V
C
Boosting the LF156 with a Current Amplifier
PU
(R8
e
Wide BW Low Noise Low Drift Amplifier
R8 R1) C
j 150 mA (will drive R
10
a
0 15
MAX
b
R7)
2
V
e
0
2 V
s (with C
s
S
V
r
P
C s
3 Decades VCO
j 191 kHz
30V 10 Hz
L
shown)
L t
100 )
s
f
s
(Continued)
10 kHz
TL H 5646–24
12
V
Overshoot 6%
t
When driving large C
I
By adding D1 and R
by feedback path through R
Leakage of circuit is essentially I
of Cp
Diode D3 clamps V
reverse bias of D2
Maximum input frequency should be
shunt capacitance of D2
OUT(MAX)
s
OUT
T
10 s
Non-Inverting Unity Gain Operation for LF157
e
I
OUT
C
L
Isolating Large Capacitive Loads
j
Inverting Unity Gain for LF157
0 02
0 5
Low Drift Peak Detector
OUT
f
V
V
L
D1
(A1) to V
s
the V
e
e
f
0 during hold mode Leakage of D2 provided
0 04 V
OUT
b
IN
(LF155 LF156) plus capacitor leakage
b
slew rate determined by C
V
kk
s (with C
D3
to improve speed and to limit
R1C
R1
A
f
R1C
R1
A
f
b
b
V(DC)
V(DC)
3 dB
3 dB
L
e
e
R
shown)
t
t
f
C
R2
R2
4
D2
(2 ) (5 MHz)
e
(2 ) (5 MHz)
e b
a
4
1
5 MHz
5 MHz
where C
R
1
1
1
S
TL H 5646 – 22
TL H 5646 – 25
TL H 5646
D2
L
is the
and