LMC6041AIN National Semiconductor, LMC6041AIN Datasheet - Page 9

• Manufacturer Part Number: LMC6041AIN
• Description: IC OP AMP CMOS SINGL MICRO 8-DIP
• Manufacturer: National Semiconductor

Specifications of LMC6041AIN

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 0.02 V/µs
• Gain Bandwidth Product: 75kHz
• Current - Input Bias: 0.002pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 18µA
• Current - Output / Channel: 40mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 15.5 V, ±2.25 V ~ 7.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Other names: *LMC6041AIN; *LMC6041AIN/NOPB; LMC6041AIN/NOPB

Applications Hints
The effect of input capacitance can be compensated for by
adding a capacitor. Adding a capacitor, C
back resistor (as in Figure 1 ) such that:
or
Since it is often difficult to know the exact value of C
be experimentally adjusted so that the desired pulse re-
sponse is achieved. Refer to the LMC660 and the LMC662
for a more detailed discussion on compensating for input
capacitance.
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an
oscillatory or underdamped pulse response. With a few ex-
ternal components, op amps can easily indirectly drive ca-
pacitive loads, as shown in Figure 2.
FIGURE 1. Cancelling the Effect of Input Capacitance
R
1
C
IN
≤ R
2
(Continued)
C
f
f
, around the feed-
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IN
, C
f
can
9
In the circuit of Figure 2, R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency compo-
nent of the output signal back to the amplifier’s inverting
input, thereby preserving phase margin in the overall feed-
back loop.
Capacitive load driving capability is enhanced by using a pull
up resistor to V
conducting 10 µA or more will significantly improve capaci-
tive load responses. The value of the pull up resistor must be
determined based on the current sinking capability of the
amplifier with respect to the desired output swing. Open loop
gain of the amplifier can also be affected by the pull up
resistor (see Electrical Characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6041, typically less
than 2fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6041’s inputs and the
FIGURE 2. LMC6041 Noninverting Gain of 10 Amplifier,
Compensated to Handle Capacitive Loads
Capacitive Loads with a Pull Up Resistor
FIGURE 3. Compensating for Large
+
(Figure 3 ). Typically a pull up resistor
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