LTC695CSW#PBF Linear Technology, LTC695CSW#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC695CSW#PBF
• Description: IC MPU SUPERVISRY CIRCUIT 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC695CSW#PBF

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Elements: 1
• Monitored Voltage 1 (typ): 4.65V
• Battery Backup Switching: Yes
• Watchdog Timer: Yes
• Chip Enable Signals: Yes
• Reset Active Time: 280ms
• Manual Reset: No
• Package Type: SOIC W
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.75V
• Reset Threshold Voltage (min): 4.5V
• Family Name: LTC695
• Power Dissipation: 500mW
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Power Fail Detection: Yes
• Mounting: Surface Mount
• Pin Count: 16
• Supply Current: 1.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond V
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
Memory Protection
The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
by preventing write operations when V
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V
CE OUT follows CE IN with a typical propagation delay of
20ns. When V
or V
OUT is an alternative signal to drive the CE, CS, or Write
BATT
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
BATT
to GND and V
, CE OUT is forced high, independent of CE IN. CE
CC
CE OUT
10Ω
CE IN
falls below the reset voltage threshold
V
CC
V
OUT
OUT
= V
to V
4.3M
BATT
CC
.
0.1μF
CC
Figure 5. Timing Diagram for CE IN and CE OUT
V
BATT
is at invalid level.
LTC690
LTC691
LTC694
LTC695
GND
690 F04
CC
CC
V1
is 5V,
due
V2
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW⎯LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
CC
OUT
BATT
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
STATUS
C2 monitors V
V
The supply current is 1μA maximum.
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored.
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
Chip⎯Enable Input is ignored.
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored.
OSC SEL is ignored.
OUT
is connected to V
CC
for active switchover.
LTC690/LTC691
LTC694/LTC695
BATT
through an internal PMOS switch.
V
OUT
= V
690 F05
BATT
11
OUT
OUT
OUT
OUT
690fe
.
.
.
.