ADM705ARZ Analog Devices Inc, ADM705ARZ Datasheet - Page 9
![IC SUPERVISOR MPU 4.65 WD 8SOIC](/photos/5/66/56684/505-8-soic_sml.jpg)
ADM705ARZ
Manufacturer Part Number
ADM705ARZ
Description
IC SUPERVISOR MPU 4.65 WD 8SOIC
Manufacturer
Analog Devices Inc
Type
Simple Reset/Power-On Resetr
Specifications of ADM705ARZ
Number Of Voltages Monitored
1
Output
Push-Pull, Totem Pole
Reset
Active Low
Reset Timeout
160 ms Minimum
Voltage - Threshold
4.65V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Threshold Voltage
4.65V
No. Of Supervisors / Monitors
1
Supply Voltage Range
1V To 5.5V
Reset Type
Active-Low
Supply Current
190µA
Delay Time
200ms
Digital Ic Case Style
SOIC
Current, Output
20 mA
Current, Supply
190 μA
Package Type
SOIC-8
Power Dissipation
470 mW
Temperature, Operating, Range
-40 to +85 °C
Voltage, Supply
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADM705ARZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADM705ARZ-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADM705ARZ-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis can be added to
the power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input, as shown in
Figure 16
When PFO is low, Resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, Resistor R3 sources
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity can be
achieved by connecting a capacitor between PFI and GND. The
equations used to calculate the hysteresis are as follows:
7V TO 15V
POWER
V
V
V
INPUT
H
L
MID
Figure 16. Adding Hysteresis to the Power-Fail Comparator
=
=
.
R1
R2
. 1
. 1
=
PFO
25
5V
0V
25
. 1
25
0V V
+
⎡
⎢
⎣
ADP3367
1
⎛
⎜
⎝
R1
+
R1
L
⎛
⎜
⎝
⎛
⎜
⎝
R2
. 1
R2
R2
V
+
R2
IN
25
R2
PFI
V
×
+
ADM705/ADM706/
ADM707/ADM708
H
−
5V
R3
1.25V
R3
⎞
⎟
⎠
V
⎞
⎟
⎠
CC
R1
V
R3
−
CC
⎤
⎥
⎦
–
+
. 1
25
R3
⎞
⎟
⎠
PFO
TO
MICROPROCESSOR
NMI
Rev. G | Page 9 of 12
VALID RESET BELOW 1 V V
The ADM705/ADM706/ADM707/ADM708 are guaranteed to
provide a valid reset level with V
Performance Characteristics section). As V
the internal transistor does not have sufficient drive to hold the
voltage RESET at 0 V. A pull-down resistor can be connected
externally, as shown in
required.
ADM705/ADM706/ADM707/ADM708
ADM705/ADM706/
ADM707/ADM708
Figure 17. RESET Valid Below 1 V
Figure 17
GND
RESET
CC
, to hold the line low if
CC
as low as 1 V (see the Typical
R1
CC
drops below 1 V,