MAX16005ETE+ Maxim Integrated Products, MAX16005ETE+ Datasheet - Page 7
![IC UP SUPERVISOR HEX 16-TQFN](/photos/6/66/66625/16-tqfn_exp_pad_21-0136_sml.jpg)
MAX16005ETE+
Manufacturer Part Number
MAX16005ETE+
Description
IC UP SUPERVISOR HEX 16-TQFN
Manufacturer
Maxim Integrated Products
Type
Multi-Voltage Supervisorr
Datasheet
1.MAX16000ETC.pdf
(26 pages)
Specifications of MAX16005ETE+
Number Of Voltages Monitored
6
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
6 Selectable Threshold Combinations
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Monitored Voltage
Adjustable
Undervoltage Threshold
Adjustable
Overvoltage Threshold
Adjustable
Output Type
Active Low, Open Drain
Manual Reset
Resettable
Watchdog
Watchdog
Battery Backup Switching
No Backup
Power-up Reset Delay (typ)
280 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Supply Current (typ)
50 uA
Maximum Power Dissipation
1349 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Power Fail Detection
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10
11
12
—
—
—
—
—
1
2
3
4
5
6
7
8
9
PIN
10
11
12
14
15
16
13
—
1
2
4
5
6
7
3
8
9
—
—
—
—
10
11
12
—
1
2
4
5
8
3
6
7
9
_______________________________________________________________________________________
MARGIN
RESET
NAME
Low-Voltage, Quad-/Hex-/Octal-Voltage
OUT3
OUT4
OUT2
OUT1
GND
V
TOL
WDI
SRT
IN3
IN4
IN1
IN2
MR
EP
CC
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
Ground
Unmonitored Power-Supply Input
O utp ut 3. When the vol tag e at IN 3 fal l s b el ow i ts thr eshol d , OU T3 g oes l ow and stays l ow unti l the
vol tag e at IN 3 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
O utp ut 4. When the vol tag e at IN 4 fal l s b el ow i ts thr eshol d , OU T4 g oes l ow and stays l ow unti l the
vol tag e at IN 4 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
O utp ut 2. When the vol tag e at IN 2 fal l s b el ow i ts thr eshol d , OU T2 g oes l ow and stays l ow unti l the
vol tag e at IN 2 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
O utp ut 1. When the vol tag e at IN 1 fal l s b el ow i ts thr eshol d , OU T1 g oes l ow and stays l ow unti l the
vol tag e at IN 1 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL
to V
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the first
transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The
WDI open-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most
three-state drivers exceeds 200nA.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the
reset timeout period after MR is deasserted. MR is pulled up to V
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period.
The reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10
connect SRT to V
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective thresholds and MR is deasserted. This
open-drain output has a 30µA internal pullup.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a
low thermal resistance path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
CC
Pin Description (MAX16000/MAX16001/MAX16002)
to select 10% threshold tolerance.
CC
.
6
(Ω) x C
SRT
(F). For the internal timeout period of 140ms (min),
FUNCTION
µP Supervisors
CC
through a 20kΩ resistor.
C C
C C
C C
C C
.
.
.
.
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