MAX16048ACB+ Maxim Integrated Products, MAX16048ACB+ Datasheet - Page 50

• Manufacturer Part Number: MAX16048ACB+
• Description: IC EE-PROG SYS MGR 8CH 64-TQFP
• Manufacturer: Maxim Integrated Products
• Type: System Managerr

Specifications of MAX16048ACB+

• Number Of Voltages Monitored: 8
• Output: Open Drain, Push-Pull
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
The MAX16046A/MAX16048A feature an I
compatible 2-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX16046A/MAX16048A and the master device at
clock rates up to 400kHz. Figure 1 shows the 2-wire
interface timing diagram. The MAX16046A/MAX16048A
are transmit/receive slave-only devices, relying upon a
master device to generate a clock signal. The master
device (typically a microcontroller) initiates a data
transfer on the bus and generates SCL to permit that
transfer.
A master device communicates to the MAX16046A/
MAX16048A by transmitting the proper address followed
by command and/or data words. The slave address
input, A0, is capable of detecting four different states,
allowing multiple identical devices to share the same seri-
al bus. The slave address is described further in the
Slave Address section. Each transmit sequence is framed
by a START (S) or REPEATED START (SR) condition and
a STOP (P) condition. Each word transmitted over the bus
is 8 bits long and is always followed by an acknowledge
pulse. SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ for
most applications.
Figure 9. Bit Transfer
50
SDA
SCL
______________________________________________________________________________________
DATA LINE STABLE,
DATA VALID
DATA ALLOWED
CHANGE OF
I
2
C/SMBus-Compatible
Serial Interface
2
C/SMBus-
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 9);
otherwise the MAX16046A/MAX16048A registers a
START or STOP condition (Figure 10) from the master.
SDA and SCL idle high when the bus is not busy.
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master device issues
a STOP condition by transitioning SDA from low to high
while SCL is high. A STOP condition frees the bus for
another transmission. The bus remains active if a
REPEATED START condition is generated, such as in
the block read protocol (see Figure 1).
The MAX16046A/MAX16048A recognize a STOP condi-
tion at any point during transmission except if a STOP
condition occurs in the same high pulse as a START
condition. This condition is not a legal I
one clock pulse must separate any START and STOP
condition.
A REPEATED START may be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START condi-
tions are functionally identical.
Figure 10. START and STOP Conditions
SDA
SCL
CONDITION
START
S
REPEATED START Conditions
START and STOP Conditions
Early STOP Conditions
2
C format; at least
Bit Transfer
CONDITION
STOP
P