MIC705M Micrel Inc, MIC705M Datasheet - Page 6
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MIC705M
Manufacturer Part Number
MIC705M
Description
IC SUPERVISOR 4.65V VTH 8-SOIC
Manufacturer
Micrel Inc
Type
Simple Reset/Power-On Resetr
Datasheet
1.MIC705MY.pdf
(7 pages)
Specifications of MIC705M
Number Of Voltages Monitored
1
Reset
Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.65V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Threshold Voltage
4.65V
No. Of Supervisors / Monitors
1
Supply Voltage Range
1.4V To 5.5V
Reset Type
Manual, Active-Low
Supply Current
60µA
Delay Time
200ms
Digital Ic Case Style
SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Output
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MIC705M
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Part Number:
MIC705MY
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
MIC705/06/07/08
Applications Information
Battery Switchover Section
The MIC691/693 monitors the supply voltage applied to the
V
and V
happens, the auxiliary supply on V
low impedance PMOS switch to the VOUT pin. The V
is capable of sourcing up to 25mA when in the backup mode.
V
normal operation (V
currents of up to 250mA. V
RAM. The BATT ON Pin can be used to indicate the status
of battery backup mode or as the base drive for an external
pass transistor when V
in battery-backup mode. V
substrate whenever V
V
0.6V above V
conduct from the V
Microprocessor Reset
The /RESET pin is asserted whenever V
reset threshold voltage. The reset pin remains asserted for a
period of 200ms after VCC has risen above the reset thresh-
old voltage. The reset timeout period can also be selected
by the end user, see Table 1. The reset function ensures the
microprocessor is properly reset and powers up into a known
condition after a power failure. /RESET will remain valid with
VCC as low as 1.4V and when auxiliary power is connected
to VBATT (VBATT > 2.0V), the reset pin will remain valid with
VCC from 0V to 5.5V.
Chip Enable Gating
The MIC691/693 also include memory protection circuitry
which inhibits the writing of memory during a power fail con-
dition. During normal operation, chip enable transitions are
gated througha series transmission gate from /CE IN to /CE
OUT. The typical propagation delay through the chip enable
gating circuitry is 2ns. /CE OUT follows /CE IN unless V
drops below the reset threshold voltage, at which time /CE OUT
will remain high until V
can be write protected in a similar manner by connecting the
/CE OUT pin to the store or write input.
MIC705/06/07/08
CC
CC
BATT
pin. Whenever V
is routed to V
BATT
is connected to a voltage source that is greater than
, the device enters battery-backup mode. When this
CC
, the parasitic diode of the V
OUT
BATT
CC
CC
CC
through a large PMOS switch during
> V
CC
falls below the reset threshold voltage
OUT
to the substrate.
returns to a valid level. EEPROMs
BATT
CC
exceeds the reset threshold. If
OUT
has to source more than 25mA
is connected to V
) and can source continuous
can be used to drive CMOS
BATT
is routed through a
CC
BATT
falls below the
OUT
switch will
and the
OUT
pin
CC
6
Power Fail Warning
An additional comparator which is independent of the other
functions on the MIC691/693 is provided for early warning
of power failure. An external voltage divider can be used to
compare unregulated DC to an internal 1.25V reference. The
voltage divider ratio on the input of the power-fail comparator
(PFI) can be chosen so as to trip the power fail comparator a
few milliseconds before V
threshold voltage. The output of the power-fail comparator
(/PFO) can be used to interrupt the microprocessor when
used in this mode and execute shut-down procedures prior
to power loss. Hysteresis can be added to this comparator
with external resistors, as is commonly done with any com-
parator. When VCC < VBATT - 1.2V (typ.), the power-fail
comparator is turned off and /PFO is pulled low in order to
conserve power.
Watchdog Timer
The microprocessor can be monitored by connecting the
WDI pin (watchdog input) to a bus line or an I/O line. If a
transition doesn't occur on the WDI pin with in the watchdog
timeout (Table 1.), the microprocessor is reset. /RESET will
remain asserted for 200ms when this occurs. A minimum
pulse of 100ns or any transition low-to-high or high-to-low
on the WDI pin will reset the watchdog timer. The output of
the watchdog timer (WDO) will remain high, if WDI sees a
valid transition within the watchdog period or if VCC falls
below the reset threshold as the watchdog timer is disabled
when this happens.
Unregulated DC
R1
R2
Power Fail Comparator
PFI
CC
1.25V
falls below the maximum reset
+
-
January 2006
PFO
Micrel, Inc.