MAX707ESA-T ON Semiconductor, MAX707ESA-T Datasheet - Page 7

• Manufacturer Part Number: MAX707ESA-T
• Description: IC MPU SUPERVISORY 4.63V 8SOIC
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of MAX707ESA-T

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.63V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MAX707ESA-TOS

RESET Signal Integrity During Power−Down
below 1.0 V. Then, the output becomes an open circuit and
no longer sinks current. This means CMOS logic inputs of
the mP will be floating at an undetermined voltage. Most
digital systems are completely shutdown well above this
voltage. However, in the case RESET must be maintained
valid to V
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 14). This resistor value, though
not critical, should be chosen large enough not to load
RESET and small enough to pull it to ground. R = 100 kW
will be suitable for most applications.
Interfacing with mPs with Bidirectional I/O Pins
the RESET output is driven high and the mP wants to put it
low, indeterminate logic level may result. This can be
avoided by adding a 4.7 kW resistor in series with the output
of the MAX707/708 (Figure 15). If there are other
components in the system that require a reset signal, they
should be buffered so as not to load the reset line. If the other
The MAX707/708 RESET output is valid until V
Some mPs have bidirectional reset pins. If, for example,
Figure 14. Ensuring RESET Valid to V
CC
V
CC_1
= 0 V, a pull down resistor must be connected
R1
R2
MAX707/708
GND
V CC
RESET
PFI
MAX707/708
V
V CC
GND
CC_2
RESET
R3
PFO
Figure 16. Monitoring Additional Supply Levels
MR
100 k
R
RESET
CC
V
GND
= 0 V
V CC
CC_3
m P
MAX707, MAX708
CC
http://onsemi.com
falls
7
components are required to follow the reset I/O of the mP, the
buffer should be connected as shown with the solid line.
Monitoring Additional Supply Levels
properly, you can monitor a voltage different than the
unregulated DC one. As shown in Figure 16, to increase
noise immunity, hysteresis may be added to the power−fail
comparator just by a resistor between PFO and PFI. Not to
unbalance the potential divider network, R3 should be 10
times the sum of the two resistors R1 and R2. If required, a
capacitor between PFI and GND will reduce the sensitivity
of the circuit to high−frequency noise on the line being
monitored. The PFO output may be connected to MR input
to generate a low level on the RESET when V
of tolerance. Thus a RESET is generated when one of the
two voltages is below its threshold level.
MAX707/708
When connecting a voltage divider to PFI and adjusting it
Figure 15. Interfacing to Bidirectional Reset I/O
V CC
GND
RESET
V L + 1.25 ) R1
V H + 1.25
V HYS + V H * V L +
V
CC_2
PFO
0 V
4.7 k
0 V
(1 ) R1
BUFFER
V
RESET
L
V
1.25
CC_1
R2
R1
GND
V CC
m P
V
)
H
R2 ) R3
R2
R3
V cc_2
1.25 * V cc_2
R3
BUFFERED
RESET TO
OTHER SYSTEM
COMPONENTS
R3
CC
)
_1
drops out