LT3070EUFD#PBF Linear Technology, LT3070EUFD#PBF Datasheet

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FeAtures Output Current Dropout Voltage: 85mV Typical n Digitally Programmable V : 0.8V to 1.8V n OUT Digital Output Margining: ±1%, ±3% or ±5% n Low Output Noise: 25µV (10Hz to 100kHz) n RMS Parallel Multiple Devices for ...

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... Output Short-Circuit Duration……...................Indefinite Operating Junction Temperature (Note 2) LT3070E/LT3070I ............................. –40°C to 125°C LT3070MP ......................................... –55°C to 125°C Storage Temperature Range .................. –65°C to 150°C orDer inFormAtion LEAD FREE FINISH TAPE AND REEL LT3070EUFD#PBF LT3070EUFD#TRPBF LT3070IUFD#PBF LT3070IUFD#TRPBF LT3070MPUFD#PBF LT3070MPUFD#TRPBF LEAD BASED FINISH TAPE AND REEL ...

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T otherwise noted. PARAMETER CONDITIONS IN Pin Voltage Range V ≥ BIAS Pin Voltage Range (Note 3) Regulated Output Voltage V = 0.8V, 10mA ≤ I OUT V = 0.9V, 10mA ≤ I OUT V = 1V, 10mA ≤ I OUT V = 1.1V, 10mA ≤ I OUT V = 1.2V, 10mA ≤ I OUT V = 1.5V, 10mA ≤ I OUT V = 1.8V, 10mA ≤ I OUT ...

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LT3070 electricAl chArActeristics temperature range, otherwise specifications are at T otherwise noted. PARAMETER CONDITIONS BIAS Pin Current in Nap Mode EN = Low (After POR Completed) BIAS Pin Current 10mA OUT V = 1.3V 100mA IN OUT OUT I = 500mA OUT OUT I = 2.5A OUT OUT ...

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T otherwise noted. PARAMETER CONDITIONS V Ripple Rejection V BIAS BIAS V – Ripple Rejection V = 2.5V BIAS (Notes – Reference Voltage Noise C REF/BYP (REF/BYP Pin) Output Voltage Noise V = 1V, I OUT BW = 10Hz to 100kHz ...

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LT3070 typicAl perFormAnce chArActeristics Dropout Voltage vs I OUT 150 OUT(NOMINAL 25°C J 120 1.8V OUT V = 3.3V BIAS 0.8V OUT V = 2.5V BIAS 30 0 ...

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Output Voltage (1.8V) vs Temperature 1.818 I = 10mA LOAD 1.814 1.810 1.806 1.802 1.798 1.794 1.790 1.786 1.782 –75 –50 – 100 125 150 TEMPERATURE (°C) 3070 G10 BIAS Pin Current in ...

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LT3070 typicAl perFormAnce chArActeristics Logic Input Threshold Voltages Logic Low to Hi-Z State Transitions 0.8 SEE APPLICATIONS INFORMATION FOR MORE DETAILS 0.7 INPUT RISING LOGIC LOW TO Hi-Z 0.6 INPUT FALLING 0.5 LOGIC Hi-Z TO LOW 0.4 0.3 –75 –50 ...

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BIAS Pin Ripple Rejection 100 OUT OUT 10µF + 4.7µF + 2.2µF OUT 2.5V + ...

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LT3070 typicAl perFormAnce chArActeristics Input Voltage Line Regulation 300 V = 3.3V BIAS V = 1.05V TO 2.7V IN 250 V = 0.8V OUT I = 10mA OUT 200 150 100 50 0 –75 –50 – ...

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Bias Voltage Line Transient Response V OUT 10mV/DIV V BIAS 200mV/DIV 3070 G43 V = 1.3V 20µs/DIV 2.5V BIAS OUT OUT C = 16.9µF OUT Transient Load Response ...

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LT3070 pin Functions VIOC (Pin 1): Voltage for In-to-Out Control. The IC in- corporates a unique tracking function to control a buck regulator powering the LT3070’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3070’s input voltage at V 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information sec- tion for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an open- drain NMOS output that actively pulls low if any one of these fault modes is detected: • less than 90 OUT OUT(NOMINAL) edge OUT • V drops below 85 OUT OUT(NOMINAL) 25µs. ...

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Functions + V BIAS BIAS EN SENSE IN OUT LT3070 PWRGD MARGSEL IN MARGTOL VIOC REF/BYP GND Figure 1. Kelvin Sense Connection MARGSEL (Pin 21): Margining Enable and Polarity Selec- tion. This three-state pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 250mV referenced to GND and en- ables negative voltage margining. The logic high t hreshold ...

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LT3070 block DiAgrAm UVLO AND BIAS 27 THERMAL SHUTDOWN IN 5-8 – VIOC 1 + GND 4,9-14,20,26, MARGSEL OR MARGTOL  REF/BYP + EAMP – BUF LDO CORE V + 300mV OUT(NOM) ...

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ApplicAtions inFormAtion Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high cur- rent, very high speed regulator circuits that operate at low input and output voltages. The LT3070 is a low voltage, UltraFast transient response linear regulator. The device supplies output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µV (BW = 10Hz to 100kHz). The LT3070’s high RMS bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15µF minimum), saving bulk capacitance, PCB area and cost. The LT3070’s features permit state-of-the-art linear regula- tor performance. The LT3070 is ideal for high performance FPGAs, microprocessors, sensitive communication sup- plies, and high current logic applications that also operate over low input and output voltages. ...

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LT3070 ApplicAtions inFormAtion component cost savings. The LT3070 steps to the next level of performance for the latest generation FPGAs, DSPs and microprocessors. The simple versatility and benefits derived from these circuits exceed the power supply needs of today’s high performance microprocessors. Programming Output Voltage Three tri-level input pins value of output voltage. Table 1 illustrates the 3-bit digital word to output voltage resulting from setting these pins high, low or allowing them to float. These pins may be tied high or low by either pin-strapping them driving them with digital ports. Pins that BIAS float may either actually float or require logic that has Hi-Z output capability. This allows output voltage to be dynamically changed if necessary. Output voltage is selectable from a minimum of 0.8V to ...

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ApplicAtions inFormAtion The MARGTOL pin selects the absolute value of margin- ing (1 5%) if enabled by the MARGSEL input. The logic low threshold is less than 250mV referenced to GND and enables either ±1% change the state of the MARGSEL pin. The logic high threshold is greater than V – 250mV and enables either ±5% BIAS change in V depending on the state of the MARGSEL OUT pin. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and enables either ±3% change in V state of the MARGSEL pin. Table 2: Programming Margining MARGSEL MARGTOL ...

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LT3070 ApplicAtions inFormAtion SWITCHING REGULATOR + REF – PWRGD—Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is de- tected: • less than 90 OUT OUT(NOMINAL) edge OUT • V drops below 85 OUT OUT(NOMINAL) 25µs. • less than its undervoltage lockout threshold. BIAS • The OUT-to-IN reverse-current detector activates. • Junction temperature exceeds 145°C typically.* *The junction temperature detector is an early warning indicator that trips approximately 20°C before thermal shutdown engages. Stability and ...

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ApplicAtions inFormAtion inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, f form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5mΩ to 20mΩ) have some benefit in dampening the resonant loop, but higher ESRs degrade the capacitor response to transient load steps with rise/fall times less than 1µs. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale the same case size. Under these conditions, the R individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15µF is 10µF + 4.7µF + 2.2µF . Capacitors with case sizes larger than 0805 have higher ESL and lower ESR (<5mΩ). Therefore, more capacitors with smaller values (<10µF) must be chosen. Users should consider new generation, low inductance capacitors to push out f and maximize stability. Refer to the surface R mount ceramic capacitor manufacturer’s data sheets for capacitor specifications. Figure 3 illustrates an optimum ...

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LT3070 ApplicAtions inFormAtion 20 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF 0 X5R –20 –40 –60 Y5V –80 –100 BIAS VOLTAGE (V) Figure 4. Ceramic Capacitor DC Bias Characteristics 40 BOTH CAPACITORS ...

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ApplicAtions inFormAtion Load Regulation The LT3070 provides a Kelvin sense pin for V the application to correct for parasitic package and PCB I-R drops. However, LTC recommends that the SENSE pin terminate in close proximity to the LT3070’s OUT pins. This minimizes parasitic inductance and optimizes regula- tion. The LT3070 handles moderate levels of output line impedance, but excessive impedance between V C causes excessive phase shift in the feedback loop OUT and adversely affects stability. Figure 1 in the Pin Functions section illustrates the Kelvin- Sense connection method that eliminates voltage drops due to PCB trace resistance. However, note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically at V typically 1.8V. OUT Short-Circuit and Overload Recovery Like many IC power regulators, the LT3070 has safe op- erating area (SOA) protection. The safe area protection decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage up to the absolute maximum voltage rating. V the UVLO threshold for any function. The LT3070 has a precision current limit specified at ±20% that is active above UVLO. BIAS ...

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LT3070 ApplicAtions inFormAtion heat sink resistance or circuit board to ambient as the application dictates. Also, consider additional heat sources mounted in proximity to the LT3070. The LT3070 is a surface mount device and as such, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Surface mount heat sinks and plated through-holes can also be used to spread the heat generated by power devices. Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resis- tance path for heat flow. Proper mounting is required to ensure the best possible thermal flow from this area of the package to the heat sinking material. Note that the exposed pad is electrically connected to GND. Table 3 lists thermal resistance as a function of copper ...

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ApplicAtions inFormAtion Keep this ballast trace area free of solder to maintain a controlled resistance. Table 4 shows a simple guideline for PCB trace resistance as a function of weight and trace width. Table 4. PC Board Trace Resistance WEIGHT (Oz) 100 MIL WIDTH* 1 5.43 2 2.71 *Trace resistance is measured in milliohms/in Quieting the Noise The LT3070 offers numerous noise performance advan- tages. Each LDO has several sources of noise. An LDO’s most critical noise source is the reference, followed by the LDO error amplifier. Traditional low noise regulators buffer the voltage reference out to an external pin (usually through a large value resistor) to allow for bypassing and V 2. 1.5V noise reduction of reference noise. The LT3070 deviates from ...

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LT3070 ApplicAtions inFormAtion V BIAS 3.3V 47µ 0.1µF PGOOD RUN PV IN SGND PLLLPF LTC3415EUHF NC CLKOUT PHMODE NC CLKIN MODE PGND PGND PGND NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND ...

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ApplicAtions SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 V IN1 10µF SV IN1 RUN1 PLLLPF1 MODE1 PHMODE1 TRACK1 PGOOD1 LTM4616 V IN2 10µF SV IN2 RUN2 PLLLPF2 MODE2 PHMODE2 TRACK2 PGOOD2 SW2 SGND1 GND1 ...

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LT3070 pAckAge Description 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 TOP MARK (NOTE 6) 5.00 0.10 (2 SIDES) ...

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... REV DATE DESCRIPTION A 5/10 Entire data sheet revised Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LT3070 PAGE NUMBER 3070fa  ...

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... RMS IN = 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V, OUT(MIN 35.7V, Current-Based Reference with OUT Set; Directly Parallelable (No Op Amp Required), OUT : 0V to 35.7V, Current-Based Reference with OUT Set; Directly Parallelable (No Op Amp Required), OUT = 0.1V 950µA, Stable with 10µF Ceramic Capacitors 0510 REV A • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2009 , RMS , RMS , RMS 3070fa ...