LP3996SD-1833/NOPB National Semiconductor, LP3996SD-1833/NOPB Datasheet - Page 14

• Manufacturer Part Number: LP3996SD-1833/NOPB
• Description: IC REG LDO 300/150MA DUAL 10-LLP
• Manufacturer: National Semiconductor

Specifications of LP3996SD-1833/NOPB

• Regulator Topology: Positive Fixed
• Voltage - Output: 1.8V, 3.3V
• Voltage - Input: 2 ~ 6 V
• Voltage - Dropout (typical): -, 0.21V @ 300mA
• Number Of Regulators: 2
• Current - Output: 150mA (Min), 300mA (Min)
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-LLP
• For Use With: LP3996SD-3333EV - BOARD EVALUATION LP3996SD-3333LP3996SD-3033EV - BOARD EVALUATION LP3996SD-3033LP3996SD-3030EV - BOARD EVALUATION LP3996SD-3030LP3996SD-2828EV - BOARD EVALUATION LP3996SD-2828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: LP3996SD-1833; LP3996SD-1833; LP3996SD-1833TR

www.national.com
costly) than a ceramic capacitor with the same ESR value. It
should also be noted that the ESR of a typical tantalum will
increase about 2:1 as the temperature goes from 25°C down
to -40°C, so some guard band must be allowed.
ENABLE CONTROL
The LP3996 features active high enable pins for each regu-
lator, EN1 and EN2, which turns the corresponding LDO off
when pulled low. The device outputs are enabled when the
enable lines are set to high. When not enabled the regulator
output is off and the device typically consumes 2nA.
If the application does not require the Enable switching fea-
ture, one or both enable pins should be tied to V
regulator output permanently on.
To ensure proper operation, the signal source used to drive
the enable inputs must be able to swing above and below the
specified turn-on / off voltage thresholds listed in the Electrical
Characteristics section under V
POWER-ON-RESET
The POR pin is an open-drain output which will be set to Low
whenever the output of LDO2 falls out of regulation to ap-
proximately 90% of its nominal value. An external pull-up
resistor, connected to V
During start-up, or whenever a fault condition is removed, the
POR flag will return to the High state after the output reaches
approximately 96% of its nominal value. By connecting a ca-
pacitor from the SET pin to GND, a delay to the rising condi-
tion of the POR flag may be introduced. The delayed signal
may then be used as a Power-on -Reset for a microprocessor
within the user's application.
The duration of the delay is determined by the time to charge
the delay capacitor to a threshold voltage of 1.25V at 1.2µA
from the SET pin as in the formula below.
OUT
or V
IL
and V
IN
, is required on this pin.
IH
.
IN
to keep the
14
A 0.1µF capacitor will introduce a delay of approximately
100ms.
BYPASS CAPACITOR
The internal voltage reference circuit of the LP3996 is con-
nected to the C
external capacitor, connected to this pin, forms a low-pass
filter which reduces the noise level on both outputs of the de-
vice. There is also some improvement in PSSR and line
transient performance. Internal circuitry ensures rapid charg-
ing of the C
ceramic capacitor with either NPO or COG dielectric is rec-
ommended due to their low leakage characteristics and low
noise performance.
SAFE AREA OF OPERATION
Due consideration should be given to operating conditions to
avoid excessive thermal dissipation of the LP3996 or trigger-
ing its thermal shutdown circuit. When both outputs are en-
abled, the total power dissipation will be P
Where P
In general, device options which have a large difference in
output voltage will dissipate more power when both outputs
are enabled, due to the input voltage required for the higher
output voltage LDO. In such cases, especially at elevated
ambient temperature, it may not be possible to operate both
outputs at maximum current at the same time.
D
= (V
BYP
IN
capacitor during start-up. A 10nF, high quality
BYP
- V
pin via a high value internal resistor. An
OUT
) x I
OUT
for each LDO.
20145841
D(LDO1)
+ P
D(LDO2)