S-1165B30MC-N6PTFG Seiko Instruments, S-1165B30MC-N6PTFG Datasheet - Page 13

• Manufacturer Part Number: S-1165B30MC-N6PTFG
• Description: IC REG LDO 200MA 3.0V SOT23-5
• Manufacturer: Seiko Instruments

Specifications of S-1165B30MC-N6PTFG

• Regulator Topology: Positive Fixed
• Voltage - Output: 3V
• Voltage - Input: Up to 6.5V
• Voltage - Dropout (typical): 0.14V @ 200mA
• Number Of Regulators: 1
• Current - Output: 200mA (Min)
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6.5 V
• Output Voltage: 3 V
• Output Type: Fixed
• Dropout Voltage (max): 0.2 V at 200 mA
• Output Current: 200 mA
• Line Regulation: 0.2 % / V
• Load Regulation: 40 mV
• Voltage Regulation Accuracy: 1 %
• Maximum Power Dissipation: 0.3 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The S-1165 Series performs phase compensation using the internal phase compensator in the IC and the ESR
(Equivalent Series Resistance) of the output capacitor to enable stable operation independent of changes in the
output load. Therefore, always place a capacitor (C
For stable operation of the S-1165 Series, it is essential to employ a capacitor whose ESR is within an optimum
range. Using a capacitor whose ESR is outside the optimum range (approximately 0.5 to 5 Ω), whether larger
or smaller, may cause an unstable output, resulting in oscillation. For this reason, a tantalum electrolytic
capacitor is recommended.
When a ceramic capacitor or an OS capacitor with a low ESR is used, it is necessary to connect an additional
resistor that serves as the ESR in series with the output capacitor.
approximately 0.5 to 5 Ω, which varies depending on the usage conditions, so perform sufficient evaluation for
selection. Ordinarily, around 1.0 Ω is recommended.
Note that an aluminum electrolytic capacitor may increase the ESR at a low temperature, causing oscillation.
When using this kind of capacitor, perform thorough evaluation, including evaluation of temperature
characteristics.
Rev.4.0
Selection of Output Capacitor (C
3. Shutdown pin (ON/OFF pin)
The structure of the ON/OFF pin is as shown in Figure 12. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption
increases if a voltage of 0.3 V to V
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-
in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially
reduce the current consumption. The VOUT pin becomes the V
resistance of several hundreds kΩ between the VOUT pin and VSS pin.
used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.
Logic Type
ON/OFF
_00
A
A
B
B
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Figure 12
“H”: Power off
“H”: Power on
“L”: Power on
“L”: Power off
ON/OFF Pin
VSS
VIN
Internal Circuits
IN
– 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not
Operating
Operating
Stopped
Stopped
Seiko Instruments Inc.
L
)
Table 5
L
) of 2.2 μF or more between VOUT and VSS pins.
VOUT Pin Voltage
Set value
Set value
V
V
SS
SS
level
level
SS
level due to the internally divided
The required resistance value is
Current Consumption
I
I
I
I
SS1
SS2
SS2
SS1
S-1165 Series
13