LT4356HS-3#TRPBF Linear Technology, LT4356HS-3#TRPBF Datasheet - Page 15
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LT4356HS-3#TRPBF
Manufacturer Part Number
LT4356HS-3#TRPBF
Description
IC REG OVP FAULT TIMER 16SOIC
Manufacturer
Linear Technology
Datasheet
1.LT4356HDE-3PBF.pdf
(24 pages)
Specifications of LT4356HS-3#TRPBF
Voltage - Working
4 ~ 80V
Voltage - Clamping
27V Adj
Technology
Mixed Technology
Number Of Circuits
1
Applications
Automotive
Package / Case
16-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIONS INFORMATION
Shutdown
The LT4356-3 can be shut down to a low current mode
when the voltage at the SHDN pin goes below the shutdown
threshold of 0.6V. The quiescent current drops to 7μA. All
functions are turned off including the auxiliary amplifi er.
After the GATE pin pulls low due to a fault time out, the
LT4356-3 latches off. Allow suffi cient time for the TMR pin
to discharge to 0.5V (typical discharge current is 2.2μA)
and for the MOSFET to cool before attempting to reset the
part. To reset, pull the SHDN pin low for at least 100μs,
then pull high with a slew rate of at least 10V/ms.
The SHDN pin can be pulled up to V
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1μA
if no pull up device is used to help turn it on.
Supply Transient Protection
The LT4356-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Nevertheless,
voltage transients above 100V may cause permanent dam-
age. During a short-circuit condition, the large change in
current fl owing through power supply traces and associated
wiring can cause inductive voltage transients which could
SMAJ58CA
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
12V
V
D2*
IN
*DIODES INC.
10mΩ
11
12
R
6
7
SNS
V
SHDN
A
IN
SNS
CC
OUT
+
5
Si4435
Q2
GND
R6
10k
10
1N5245
LT4356DE-3
15V
D1
TMR
1
C
0.1μF
TMR
IRLR2908
GATE
Q1
4
R3
10Ω
CC
OUT
43563 F08
FLT
EN
FB
3
or below GND by
2
8
9
R1
59k
R2
4.99k
V
12V, 3A
CLAMPED AT 16V
OUT
exceed 100V. To minimize the voltage transients, the power
trace parasitic inductance should be minimized by using
wide traces. A small surge suppressor, D2, in Figure 9,
at the input will clamp the voltage spikes.
A total bulk capacitance of at least 22μF low ESR is required
close to the source pin of MOSFET Q1. In addition, the
bulk capacitance should be at least 10 times larger than
the total ceramic bypassing capacitor on the input of the
DC/DC converter.
Layout Considerations
To achieve accurate current sensing, Kelvin connection
to the current sense resistor (R
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/square. Small resistances can cause large errors in
high current applications. Noise immunity will be improved
signifi cantly by locating resistive dividers close to the pins
with short V
Design Example
As a design example, take an application with the follow-
ing specifi cations: V
to 80V, V
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
Figure 9. Overvoltage Regulator with Low-Battery Detection
UNDERVOLTAGE
383k
100k
R4
R5
OUT
V
IN
SMAJ58A
CC
≤ 16V, current limit (I
D2
and GND traces.
12
11
6
7
V
SHDN
IN
A
CC
OUT
+
CC
10mΩ
R
SNS
GND
LT4356DE-3
= 8V to 14V DC with transient up
SNS
10
5
IRLR2908
GATE
Q1
TMR
4
R3
10Ω
1
C
47nF
SNS
TMR
OUT
43563 F09
FLT
3
EN
FB
LIM
in Figure 9) is recom-
2
9
8
) at 5A, low battery
LT4356-3
R1
59k
R2
4.99k
FAULT
*SANYO 25CE22GA
SHDN
CONVERTER
C
22μF
L
*
DC-DC
V
CC
GND
15
43563fa