ADP120-AUJZ12R7 Analog Devices Inc, ADP120-AUJZ12R7 Datasheet - Page 5

IC REG LDO 100MA 1.2V SOT23-5

ADP120-AUJZ12R7

Manufacturer Part Number
ADP120-AUJZ12R7
Description
IC REG LDO 100MA 1.2V SOT23-5
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADP120-AUJZ12R7

Regulator Topology
Positive Fixed
Voltage - Output
1.2V
Voltage - Input
2.3 ~ 5.5 V
Number Of Regulators
1
Current - Output
100mA
Current - Limit (min)
110mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
TSOT-23-5, TSOT-5, TSOP-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Dropout (typical)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADP120-AUJZ12R7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND Pins
VOUT to GND Pins
EN to GND Pins
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
formula
T
J
= T
A
+ (P
D
× θ
JA
)
A
) and power dissipation (P
J
is within the specified temperature
D
), and the junction-to-ambient
J
JA
) is calculated from the
).
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
D
) using the
A
), the
J
) of
Rev. A | Page 5 of 20
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The speci-
fied values of θ
Refer to JESD 51-7 and JESD 51-9 for detailed information
regarding board construction. For additional information, see
Application Note AN-617, MicroCSP
Package.
Ψ
with units of °C/W. Ψ
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
B
are specified for the worst-case conditions, that is, a
+ (P
JA
D
are based on a four-layer, 4 in. × 3 in. PCB.
× Ψ
JB
JB
JB
JB
. Therefore, Ψ
JB
.
)
of the package is based on modeling and
measures the component power flowing
B
) and power dissipation (P
JB
more useful in real-world
JB
TM
thermal paths include
JA
Wafer Level Chip Scale
θ
170
260
may vary, depending on
JA
JA
) of the package is
Ψ
43
58
J
) is calculated
JB
ADP120
Unit
°C/W
°C/W
D
)

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