CS8151YDPSR7 ON Semiconductor, CS8151YDPSR7 Datasheet - Page 7

• Manufacturer Part Number: CS8151YDPSR7
• Description: IC REG LDO LIN 100MA 5V D2PAK-7
• Manufacturer: ON Semiconductor

Specifications of CS8151YDPSR7

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 6 ~ 26 V
• Voltage - Dropout (typical): 0.4V @ 100mA
• Number Of Regulators: 1
• Current - Output: 100mA
• Current - Limit (min): 100mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TO-263-7, D²Pak (7 leads + Tab), TO-263CA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS8151YDPSR7OSTR

at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100mV from the nominal value
obtained at 14V input, dropout voltage is dependent upon
load current and junction temperature.
terminals with respect to ground.
change in the input voltage. The measurement is made
under conditions of low dissipation or by using pulse
Functional Description
low current consumption mode when ever its not performing
a main routine. The Wake Up signal is generated
continuously and is used to interrupt a microcontroller that
is in sleep mode. The nominal output is a 5.0 V square wave
with a duty cycle of 50% at a frequency that is determined
by a timing capacitor, C
Wake Up output, it must issue a watchdog pulse and check
its inputs to decide if it should resume normal operations or
remain in the sleep mode.
Figure 6. Wake Up Response to RESET (Low Voltage)
Wake Up
WDI
RESET
Wake Up
Dropout Voltage: The input−output voltage differential
Input Voltage: The DC voltage applied to the input
Line Regulation: The change in output voltage for a
To reduce the drain on the battery a system can go into a
When the microprocessor receives a rising edge from the
Figure 5. Wake Up Response to WDI
Response
to RESET
Wake Up
Response
Wake Up
to WDI
Delay
.
DEFINITION OF TERMS
CIRCUIT DESCRIPTION
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7
techniques such that the average chip temperature is not
significantly affected.
change in load current at constant chip temperature.
that does not contribute to the positive load current. The
regulator ground lead current.
ripple voltage to the peak−to−peak output ripple voltage.
output.
Wake Up to go low within 2.0 ms (Typ) and remain low until
the next Wake Up cycle (see Figure 5). Other watchdog
pulses received within the same cycle are ignored (Figures
2, 3, and 4).
voltage is in regulation. During operation, if the output
voltage shifts below the regulation limits, the RESET
toggles low and remains low until proper output voltage
regulation is restored. After the RESET delay, RESET
returns high.
watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during one
Wake Up cycle will cause a RESET pulse to occur at the end
of the Wake Up cycle (see Figure 3).
regardless of the cause of the RESET. After the RESET
returns high, the Wake Up cycle begins again (see Figure 3).
RESET high to Wake Up delay time are all set by one
external capacitor C
the tolerance of the CS8151 must be taken into account in
order to get the correct system tolerance for each parameter.
Load Regulation: The change in output voltage for a
Quiescent Current: The part of the positive input current
Ripple Rejection: The ratio of the peak−to−peak input
Current Limit: Peak current that can be delivered to the
The first falling edge of the watchdog signal causes the
During power up, RESET is held low until the output
The Watchdog circuitry continuously monitors the input
The Wake Up output is pulled low during a RESET
The RESET pulse width, Wake Up signal frequency and
Wake Up Period = (4 × 10
RESET Delay Time = (5 × 10
RESET High to Wake Up Delay Time = (2 × 10
Capacitor temperature coefficient and tolerance as well as
Delay
.
5
)C
Delay
4
)C
Delay
5
)C
Delay