DLP-USB232M-G DLP Design Inc, DLP-USB232M-G Datasheet - Page 2

• Manufacturer Part Number: DLP-USB232M-G
• Description: MODULE USB-TO-TTL SRL UART CONV
• Manufacturer: DLP Design Inc
• Series: DLP-USB232Mr

Specifications of DLP-USB232M-G

• Convert From (adapter End): USB
• Convert To (adapter End): DB9 Female
• Features: Integrated 6MHz-48MHz clock multiplier PLL
• Interface Type: USB
• Data Bus Width: 8 bit
• Product: Interface Modules
• For Use With/related Products: Windows® 98 or higher, Mac OS 8.5 or higher
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 813-1018

ENHANCEMENTS
This section summarizes the enhancements of the 2nd
generation silicon from FTDI compared to its FT8U232AM
predecessor. For further details, consult the device pin-out
description and functional descriptions.
• Integrated Level Converter on UART interface and
control signals
The previous devices would drive the UART and control
signals at 5v CMOS logic levels. The new device has
a separate VCC-IO pin allowing the device to directly
interface to 3.3v and other logic families without the need
for external level converter i.c.’s.
• Improved Power Management control for USB Bus
Powered, high current devices
The previous devices had a USBEN pin, which became
active when the device was enumerated by USB. To
provide power control, this signal had to be externally
gated with SLEEP# and RESET#. This gating is now
done on-chip. USBEN has now been replaced with the
new PWREN# signal which can be used to directly drive
a transistor or P-Channel MOSFET in applications where
power switching of external circuitry is required. A new
EEPROM based option makes the device pull gently
down its UART interface lines when the power is
shut off (PWREN# is High ). In this mode, any residual
voltage on external circuitry is bled to GND when power
is removed thus ensuring that external circuitry controlled
by PWREN# resets reliably when power is restored.
Copyright © DLP Design 2002
• Lower Suspend Current
Integration of RCCLK within the device and internal
design improvements reduce the suspend current of the
FT232BM to under 200uA ( excluding the 1.5k pull-up
on USB DP ) in USB suspend mode. This allows greater
margin for peripherals to meet the USB Suspend current
limit of 500uA.
• Support for USB Isocronous Transfers
While USB Bulk transfer is usually the best choice for
data transfer, the scheduling time of the data is not
guaranteed. For applications where scheduling latency
takes priority over data integrity such as transferring
audio and low bandwidth video data, the new device now
offers an option of USB Isocronous transfer via an option
bit in the EEPROM.
• Programmable Receive Buffer Timeout
In the previous device, the receive buffer timeout used
to fl ush remaining data from the receive buffer was fi xed
at 16ms timeout. This timeout is now programmable
over USB in 1ms increments from 1ms to 255ms, thus
allowing the device to be better optimized for protocols
requiring faster response times from short data packets.
DLP-USB232M User’s Manual
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