CM1213A-04S7 ON Semiconductor, CM1213A-04S7 Datasheet - Page 7

• Manufacturer Part Number: CM1213A-04S7
• Description: TVS ARRAY ESD PROT LO 4CH SC70-6
• Manufacturer: ON Semiconductor

Specifications of CM1213A-04S7

• Voltage - Reverse Standoff (typ): 3.3V
• Voltage - Breakdown: 6V
• Power (watts): 225mW
• Polarization: 4 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant


Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between
the signal input (typically a connector) and the ESD protection device. Refer to
found., which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series
inductance back to the power supply is represented by L
where I
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact
discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here
d(I
will lead to a 300V increment in V
Similarly for negative ESD pulses, parasitic series inductance from the V
drastically increased negative voltage on the line being protected.
The CM1213A has an integrated Zener diode between V
inductance L
possible V
recommended that a 0.22µF ceramic chip capacitor be connected between V
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to
the V
planes and between the signal input and the ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection,” in the
Applications section at www.calmicro.com.
ESD
V
CL
)/dt can be approximated by ∆I
P
pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground
ESD
+ L
2
is the ESD current pulse, and V
CL
=
x d(I
, especially when V
2
Figure 3. Application of Positive ESD Pulse Between Input Channel and Ground
on V
ESD
)
Fwd
/
dt
CL
by clamping V
voltage
P
CL
is biased at a voltage significantly below the Zener breakdown voltage, it is
!
ESD
P
drop
/∆t, or 30/(1x10
at the breakdown voltage of the Zener diode. However, for the lowest
Rev. 5 | Page 7 of 14 | www.onsemi.com
SUPPLY
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of
is the positive supply voltage.
D
-9
1
). So just 10nH of series inductance (L
1
and L
P
and V
+
2
. The voltage V
N
V
. This greatly reduces the effect of supply rail
SUPPLY
+
N
P
pin to the ground rail will lead to
CL
and the ground plane.
on the line being protected is:
Error! Reference source not
L
1
x
1
d(I
and L
ESD
)
2
combined)
/
dt