ALD500RA-20SEL Advanced Linear Devices Inc, ALD500RA-20SEL Datasheet - Page 3
![no-image](/images/no-image-200.jpg)
ALD500RA-20SEL
Manufacturer Part Number
ALD500RA-20SEL
Description
IC ADC 17BIT 20SOIC
Manufacturer
Advanced Linear Devices Inc
Datasheet
1.ALD500RA-20SEL.pdf
(12 pages)
Specifications of ALD500RA-20SEL
Number Of Bits
17
Power Dissipation (max)
10mW
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
can be achieved simply and at very low cost.
An inherent benefit of the dual slope converter system is noise
immunity. The input noise spikes are integrated (averaged to
near zero) during the integration periods. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters and other high resolution
converters and perform very well in high-noise environments.
The slow conversion speed of the integrating converter provides
inherent noise rejection with at least a 20dB/decade attenuation
rate. Interference signals with frequencies at integral multiples
of the integration period are, theoretically, completely removed.
Integrating converters often establish the integration period to
reject 50/60Hz line frequency interference signals.
The relationship of the integrate and deintegrate (charge
and discharge) of the integrating capacitor values are
shown below:
Combining equations 1 and 2 results in:
where:
ALD500RAU/ALD500RA/ALD500R
V
V
V
t
t
INT
DINT
e. Very high resolution, high accuracy measurements
V
(integrate cycle)
V
(deintegrate cycle)
V
x
INT
IN
INT
X
IN
= V
/ V
= An offset voltage used as starting voltage
= Voltage change across C
= Average, or an integrated, value of input voltage
= Fixed time period over which unknown voltage is
= Unknown time period over which a known
= V
INT
during t
to be measured during t
integrated
REF
X
- (V
- (V
= -t
REF
IN
DINT
DINT
. t
ANALOG
. t
INT
INPUT
(V
(equal in magnitude)
/ t
DINT
IN
INT
)
/ R
INT
/ R
REFERENCE
VOLTAGE
INT
. C
t
INT
INT
INT
. C
INT
INT
)
(Constant V
t DINT
during t
t
DINT
)
Figure 2. Basic Dual-Slope Converter
SWITCHES
REF
V
V
IN
IN
INT
V x
1/2
V
Advanced Linear Devices
FULL SCALE
V
IN
S1
0
and
FULL SCALE
)
(1)
(2)
(3)
R
INT
POLARITY CONTROL
SWITCH DRIVER
INTEGRATOR
Actual data conversion is accomplished in two phases: Input
Signal Integration Phase and Reference Voltage Deintegration
Phase.
The integrator output is initialized to 0V prior to the start of
Input Signal Integration Phase. During Input Signal Integration
Phase, internal analog switches connect V
input where it is maintained for a fixed integration time period
(t
a digital counter
application of V
a rate determined by V
polarity of V
The Reference Voltage Deintegration Phase is initiated
immediately after t
ReferenceVoltage Deintegration Phase, internal analog
switches connect a reference voltage having a polarity opposite
that of V
digital counter controlled by the same crystal oscillator used
above is used to start counting clock pulses. The Reference
Voltage Deintegration Phase is maintained until the comparator
output inside the dual slope analog processor changes state,
indicating the integrator has returned to 0V. At that point the
digital counter is stopped. The Deintegration time period
(t
proportional to the magnitude of the applied input voltage.
After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
reset to zero through an Integrator Zero Phase and an Auto
Zero Phase so that the next conversion can begin again. In
practice, this process is usually automated so that analog-to-
digital conversion is continuously updated. The digital control
is handled by a microprocessor or a dedicated logic controller.
The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.
V
+
INT
INT
DINT
-
C
V
C
R
INT
= 4.1V MAX
REF
INT
INT
). This fixed integration period is generally determined by
), as measured by the digital counter, is directly
= Reference Voltage
= Integrating Capacitor value
= Integrating Resistor value
IN
CONTROL
V
PHASE
reference voltage is integrated
INT
to the integrator input. Simultaneously the same
IN
.
+
-
IN
MICROCONTROLLER
COMPARATOR
causes the integrator output to depart 0V at
CONTROL
(CONTROL LOGIC
A
LOGIC
+ COUNTER)
controlled by a crystal oscillator. The
DETECTION
POLARITY
INT
B
IN
, within 1 clock cycle.
and a direction determined by the
C
OUT
IN
to the buffer
During
3