78P2351-IGTR/F Maxim Integrated Products, 78P2351-IGTR/F Datasheet
78P2351-IGTR/F
Specifications of 78P2351-IGTR/F
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78P2351-IGTR/F Summary of contents
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... Earth ground structure. Reference ITU-T recommendation K.27 for more information on grounding recommendations. Page APPLICABLE DEVICES 78P2352 Dual Channel LIU 78P2351 Single Channel LIU 78P2351R Small form factor LIU 2008 Teridian Semiconductor Corp. Design Guidelines For 78P235x E4/STM1e LIUs APPLICATION NOTE AUGUST 2008 Rev 2.1 ...
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Design Guidelines for TERIDIAN 78P235x LIUs HINT: If experiencing long term bit errors in a design with isolated grounds, try connecting frame and supply grounds near the transformer with a strip of low inductance wire. SUPPLY (VCC) PLANE As with ...
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Design Guidelines for TERIDIAN 78P235x LIUs ANALOG SIGNAL TRACES AND TERMINATIONS The 78P235x LIUs have differential drivers and receivers. To maintain signal integrity and optimal performance, all differential traces should be of equal length, parallel to each other, and as ...
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Design Guidelines for TERIDIAN 78P235x LIUs All CMI coded (Analog) differential pair signal routes should have a differential trace impedance of 75 the 78P235x IC and the transformer. The termination resistors need to be placed as close as possible, and ...
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Design Guidelines for TERIDIAN 78P235x LIUs DIGITAL TRACES AND TERMINATIONS Common board design practices should be applied in the routing of high-speed clock traces. Preferably keep these signals on the top layer and their length comparable to their associated data ...
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Design Guidelines for TERIDIAN 78P235x LIUs TRANSFORMER SELECTION The 78P235x LIUs use 1:1CT (center-tapped) wide band transformers for both transmit and receive ports. These wideband transformers must exhibit the following characteristics: 75Ω impedance (primary and secondary) Max RF ...
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Design Guidelines for TERIDIAN 78P235x LIUs Figure 9. Single and Dual Core Transformer Diagrams (top view) SUPPLEMENTAL SURGE PROTECTION This section describes the recommended protection circuitry needed in order to meet the surge immunity requirements defined in the ITU ...
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Design Guidelines for TERIDIAN 78P235x LIUs RETURN LOSS MATCHING CIRCUIT Meeting the 15dB return loss requirements at the CMI-coded coax ports often requires a significant amount of engineering hours due to the unique impedance characteristics of each system design, particularly ...
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Design Guidelines for TERIDIAN 78P235x LIUs COAXIAL CONNECTORS Coaxial connectors must be of the 75-ohm variant to avoid compromising the mechanical properties of the mating receptacle and to match the impedance of the line. For optimal EMC performance and ESD ...
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Design Guidelines for TERIDIAN 78P235x LIUs PCB GUIDELINES FOR THERMALLY ENHANNCED 128-PIN LQFPS Thermally enhanced or exposed pad LQFPs have an exposed paddle or solder slug on the bottom of the package to provide the primary heat removal path. Although ...
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... Since the Transwitch L4M provides a clock for the 78P2351, the 78P2351 should be set for parallel-slave mode accordingly. The Transwitch L4M device and the 78P2351 is a 3.3V device 3.3V data buffer is needed to translate the voltages between them During L4M Line Loopback, configure the 78P2351 for Loop-timing parallel-slave mode. ...
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Design Guidelines for TERIDIAN 78P235x LIUs SAMPLE JITTER TEST RESULTS Receive Jitter Tolerance Jitter Transfer Intrinsic Transmit Jitter STM-1e FIFO enabled Filters on 0.025UIp-pk Filters off 0.053UIp-pk Page FIFO bypassed (Plesiochronous timing mode) 0.049UIp-pk 0.049UIp-pk 2008 ...
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Design Guidelines for TERIDIAN 78P235x LIUs SAMPLE TRANSMIT PULSE SHAPE RESULTS There are generally two methods for specifying and measuring the transmit pulse signal integrity. Pulse Mask Templates originate from ITU-T G.703 and Eye Diagrams originate from ANSI T1-102. Telcordia ...
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Design Guidelines for TERIDIAN 78P235x LIUs Eye Diagram The Eye Diagram provides a longer-term view of the signal, taking into account the relative time position of successive pulses. It provides less information about pulse shape but allows a more thorough ...
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Design Guidelines for TERIDIAN 78P235x LIUs The DLLs use 32 phase taps to recover a 311MHz clock (nominal phase tap spacing is 100ps). With jitter of the incoming data and variable transition density, the recovered clock will naturally hop between ...