71M6513-IGT/F Maxim Integrated Products, 71M6513-IGT/F Datasheet - Page 50
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71M6513-IGT/F
Manufacturer Part Number
71M6513-IGT/F
Description
IC ENERGY METER 3PH 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6513H-IGTF.pdf
(104 pages)
Specifications of 71M6513-IGT/F
Mounting Style
SMD/SMT
Package / Case
LQFP-100
Program Memory Size
64 KB
Program Memory Type
Flash
Supply Current (max)
6.4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6513-IGT/F
Manufacturer:
MAXIM
Quantity:
1 300
Company:
Part Number:
71M6513-IGT/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
71M6513-IGT/F
Manufacturer:
MAXIM/美信
Quantity:
20 000
Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV=0 (six mux states) and FIR_LEN = 0 (2 CK32 cycles). Since FIR filter conversions require
two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1 + 3 *
states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
Page: 50 of 104
RTM and SSI TIMING
ADC TIMING
CE TIMING
ADC EXECUTION
CE_EXECUTION
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
CE_BUSY
A Maxim Integrated Products Brand
CK32
RTM
SSI
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
S
0
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
0 0
150
LAST SSI TRANSFER
ADC0
300
CK COUNT = CE_CYCLES + floor(CE_CYCLES + 2) / 5)
1
© 2005-2011 Teridian Semiconductor Corporation
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
ADC1
600
System Timing Summary
MUX_DIV
2
Conversions (MUX_DIV=6 is shown)
ADC2
ADC MUX Frame
900
3-Phase Energy Meter IC
3
ADC3
1200
71M6513/71M6513H
4
DATA SHEET
ADC4
1500
MAX CK COUNT
BEGIN SSI TRANSFER
5
ADC5
1800
Settle
140
S
AUGUST 2011