73S8014R-DB Maxim Integrated Products, 73S8014R-DB Datasheet
73S8014R-DB
Specifications of 73S8014R-DB
Related parts for 73S8014R-DB
73S8014R-DB Summary of contents
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... TM Simplifying System Integration 73S8014R/RN/RT 20SO Demo Board User Manual July, 2008 Rev. 1.0 UM_8014_010 ...
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... Demo Board User Manual © 2008 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’ ...
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... Board Description: Jumpers, Switches and Test Points ............................................................. 10 3.2 73S8014R/RN/RT Pin Description .............................................................................................. 12 3.3 73S8014R/RN Pinout (SO20 – Top View) .................................................................................. 14 3.4 73S8014RT PINOUT (20SO – Top View) .................................................................................. 15 4 Appendix ............................................................................................................................................ 16 6 Contact Information .......................................................................................................................... 23 Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual Table of Contents ...
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... CMDVCC pin as CMDVCC% and 5V/#V as CMDVCC#. These redefined signals allow the selection of 5V, 3V and 1.8V for VCC. See the applicable data sheet for further detail. The 73S8014R uses the clock divider signals CLKDIV1 and CLKDIV2 to select between a divide and 8 for the smart card CLK output ...
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... XTAL – Illegal setting. Clock is not guaranteed to be stable as the device spec max CLK frequency is 20MHz. CLKDIV1 = CLKDIV2 = 1 - 12MHz XTAL – clock frequency = 6MHz 27MHz XTAL - clock frequency = 13.5MHz Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual clock frequency = SCLK/2 (all) clock frequency = 6MHz 5 ...
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... Demo Board User Manual 1.4 Recommended Operating Conditions and Absolute Maximum Ratings 1.4.1 Recommended Operating Conditions Parameter Supply Voltage V DD Supply Voltage V PC Ambient Operating Temperature Input Voltage for Digital Inputs 1.4.1 Absolute Maximum Ratings: Operation outside these rating limits may cause permanent damage to the device. ...
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... SCLK IOUC OFF GND 2 VPC V Power PC Supply: +4.5V to +5.5V (5V Typ.) /200mA Rev. 1.0 Figure 2: 73S8014R/RN/RT Demo Board: Basic Connections 73S8014R/RN/RT 20SO Demo Board User Manual V Power Supply +2.7V to +3.6V (3.3V Typ.) / 50mA VDD GND RSTIN CMDVCC / CMDVCC% 5V/#V / CMDVCC# CKDIV2 CKDIV1 ...
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Design Considerations 2.1 General Layout Rules Keep the CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to one layer (avoid vias to other plane). Keep CLK trace away ...
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... Note that the 3.3V power supply pin can be left open when JP3 is in position 5V. VDD voltage fault adjustment. Pin to the left is connected to the VDDF_ADJ pin of the 73S8014R/RN/RT and the pin to the right is GND. When either a resistor R3 resistor network R1 and R3 is populated on the board, it adjusts the VDD fault level that internally triggers a card deactivation sequence ...
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... Figure 3: TERIDIAN 73S8014R/RN/RT Demo Board: Board Description Rev. 1 ...
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... Crystal oscillator output: connected to the crystal. Left open if XTALIN is XTALOUT 10 being used as external clock input VDDF_ADJ 12 values (that controls deactivation of the card). Must be left open if unused. Table 4: 73S8014R/RN/RT Pin Description: Power Supply and Ground Name Pin # Description VDD 13 System interface supply voltage and supply voltage for internal circuitry. VPC 4 LDO regulator power supply source ...
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... UM_8014_010 Table 5: 73S8014R/RN/RT Pin Description: Microcontroller Interface Name Pin # CMDVCC (R) CMDVCC% 6 (RN/RT) 5V/#V (R) CMDVCC# 7 (RN/RT) CLKDIV1 20 CLKDIV2 5 OFF 1 RSTIN 2 I/OUC 3 Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual Description (R) - Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp the V activation sequence card is present ...
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... Demo Board User Manual 3.3 73S8014R/RN Pinout (SO20 – Top View) OFF 1 RSTIN 2 I/OUC 3 VPC 4 CLKDIV2 5 CMDVCC 6 5V/#V 7 GND 8 XTALIN 9 XTALOUT 73S8014R/ 16 73S8014RN UM_8014_010 CLKDIV1 PRES VCC CLK GND RST I/O VDD VDDF_ADJ GND Rev. 1.0 ...
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... UM_8014_010 3.4 73S8014RT PINOUT (20SO – Top View) OFF 1 RSTIN 2 I/OUC 3 VPC 4 CLKDIV2 5 CMDVCC% 6 CMDVCC# 7 GND 8 XTALIN 9 XTALOUT 10 Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual 73S8014RT CLKDIV1 PRES VCC CLK GND RST I/O VDD VDDF_ADJ GND 15 ...
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... Demo Board User Manual 4 Appendix This appendix includes the following tables and drawings of the PCB of the Evaluation Board: • Electrical Schematic • Bill of Materials • Silk Screen Layer – Top side • Silk Screen Layer – Bottom side • ...
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... UM_8014_010 Figure 4: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Electrical Schematic J1 SCLK 1 2 SIO 3 4 OFFB 5 GND 6 GND 7 GND 8 +5V 9 +5V 10 SSM_110_L_SV J2 SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK 1 2 S_C4 3 S_C8 5. 10uF TSM_110_01_L_SV J3 1 CLKDIV1 2 CLKDIV2 3 5V3VB/CMDVCC3B CMDVCCB/CMDVCC5B 7 RSTIN 8 9 GND 10 +3 ...
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... Demo Board User Manual Table 6: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bill of Material Item Qty Reference Part 1 3 C1, C3, C10 CAP 10UF 6.3V CERAMIC X5R 0805 2 1 C11 CAP 1.0UF 6.3V CERAMIC X5R 0603 3 2 C2, C8 CAP .1UF 16V CERAMIC X7R 0603 ...
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... UM_8014_010 Figure 5: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Top View Figure 6: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bottom View Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual 19 ...
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... Demo Board User Manual Figure 7: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Top Signal Layer Figure 8: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Middle Layer 1, Ground Plane. 20 UM_8014_010 Rev. 1.0 ...
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... UM_8014_010 Figure 9: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Middle Layer 2, Supply Plane. Figure 10: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bottom Signal Layer Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual 21 ...
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... For more information about Teridian Semiconductor products or to check the availability of the 73S8014R/RN/RT, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices http://www.teridian.com. 23 73S8014R/RN/RT 20SO Demo Board User Manual Rev. 1.0 ...
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... Demo Board User Manual Revision History Revision Date 1.0 7/3/2008 First publication. 24 UM_8014_010 Description Rev. 1.0 ...