78M6612-DB/OMU-RF Maxim Integrated Products, 78M6612-DB/OMU-RF Datasheet - Page 80
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78M6612-DB/OMU-RF
Manufacturer Part Number
78M6612-DB/OMU-RF
Description
KIT DEMO OUTLET MEAS OMU1-S-RF
Manufacturer
Maxim Integrated Products
Datasheets
1.78M6612-IMF.pdf
(111 pages)
2.78M6612-EVM-1.pdf
(58 pages)
3.78M6612-DBOMU-RF.pdf
(41 pages)
4.78M6612-DBOMU-USB.pdf
(4 pages)
Specifications of 78M6612-DB/OMU-RF
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Processor To Be Evaluated
78M6612
Data Bus Width
8 bit
Interface Type
UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
78M6612 Data Sheet
80
Name
MUX_DIV[1:0]
OPT_FDC[1:0]
RX1DIS
RX1INV
TX1E[1,0]
TX1INV
TX1MOD
PLL_OK
PLS_MAXWI DTH
[7:0]
PLS_INTERVAL
[7:0]
PLS_INV
PREBOOT
PRE_SAMPS[1:0]
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
Location
2002[7:6]
SFRB2[7]
2007[1:0]
2007[7,6]
2080[7:0]
2081[7:0]
2001[7:6]
2008[5]
2008[4]
2008[0]
2008[1]
2003[6]
2004[6]
2015
2016
2017
2018
2019
201A
201B
Rst
FF
00
0
0
0
0
0
0
0
0
0
–
0
–
–
–
–
–
–
–
Wk
00
FF
0
0
0
0
0
0
0
0
0
–
0
–
–
–
–
–
–
–
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Description
The number of states in the input multiplexer.
Selects TX1 modulation duty cycle.
RX1 can be configured as an analog input to the UART1
comparator or as a digital input/output, DIO1.
0—RX1, 1—DIO1.
Inverts result from RX1 comparator when 1. Affects only
the UART1 input. Has no effect when RX1 is used as a
DIO input.
Configures the TX1 output pin.
00—TX1, 01—DIO2, 10—WPULSE, 11—VARPULSE
Invert TX1 when 1. This inversion occurs before
modulation.
Enables modulation of TX1. When TX1MOD is set, TX1 is
modulated when it would otherwise have been zero. The
modulation is applied after any inversion caused by
TX1INV.
Indicates that system power is present and the clock
generation PLL is settled.
Determines the maximum width of the pulse (low going
pulse).
Maximum pulse width is (2*PLS_MAXWIDTH + 1)*T
Where T
the sample time (397µs). If 255, disable MAXWIDTH.
If the FIFO is used, PLS_INTERVAL must be set to 81. If
PLS_INTERVAL = 0, the FIFO is not used and pulses are
output as soon as the CE issues them.
Inverts the polarity of WPULSE and VARPULSE.
Normally, these pulses are active low. When inverted,
they become active high.
Indicates that preboot sequence is active.
The duration of the pre-summer, in samples.
The RTC interface. These are the ‘year’, ‘month’, ‘day’,
‘hour’, ‘minute’ and ‘second’ parameters of the RTC. The
RTC is set by writing to these registers. Year 00 and all
others divisible by 4 are defined as leap years.
Each write to one of these registers must be preceded by
a write to 201F (WE).
OPT_FDC
00 – Illegal
01 – 4 states
00
01
10
11
SEC 00 to 59
MIN
HR
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO
YR
I
00-42, 01-50, 10-84, 11-100.
is PLS_INTERVAL. If PLS_INTERVAL=0, T
00 to 59
00 to 23 (00=Midnight)
01 to 12
00 to 99
Function
50% Low
25% Low
12.5% Low
6.25% Low
10 – 3 states
11 – 2 states
DS_6612_001
Rev. 1.2
I
.
I
is