DEMOBOARD-U3600BM Atmel, DEMOBOARD-U3600BM Datasheet - Page 6

• Manufacturer Part Number: DEMOBOARD-U3600BM
• Description: BOARD DEMO FOR U3600BM
• Manufacturer: Atmel
• Type: Cordless Phone ICr

Specifications of DEMOBOARD-U3600BM

• Contents: Board, Software and Documentation
• For Use With/related Products: U3600BM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.3
3.4
3.5
3.6
6
Speed-up of the Loop Filter of PLL1 (“Modulator PLL”)
Speed-up of the Loop Filter of PLL3 (“1st. LO.”)
Adjustment of the Modulator Gain
Modulator PLL
U3600BM
To have a fast locking time for the modulator loop there is a precharge and a speed-up mode for
the external loop filter.
During receive mode (VCO3 enabled, VCO1 disabled) the modulator loop filter is precharged to
about half of the internally regulated 2.5V charge-pump voltage.
During the first 30 ms after enabling VCO1 the modulator phase comparator is in speed-up
mode. In this mode the current of the pase comparator which charges the loop filter is much
larger than in normal mode. Additionally to the automatically switched 30 ms speed-up mode,
the speed-up can be activated for any time by setting the bit SU1.
Similiar to PLL1, there is also a possibility to increase the locking speed of PLL3. This can be
done by setting the bit SU3. Having done this, the charge pump at the output of the phase com-
parator has a bigger current capability and therefore charges the external capacitors faster.
To fulfil the different requirements of the different countries three conversion gains of the modu-
lator are selectable by the bits GMOD [1:0] (R6: D2, D3).
Country settings see tables at channel frequencies and dividers. Ranges see electrical charac-
teristics at RF transmitter.
The fractional divider has been chosen to increase the reference frequency of the modulator
PLL.
P
Q
The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz.
In fact, the fractional divider divides Q
during 223 cycles.
For each comparison cycle (f
Q
exceeds 223, the divider divides by the value (P
value (accumulator value - 223). After 223 cycles, the correct division is executed.
557.5 kHz
Q
223
1
1
1
1
: integer part of the fractional divider (M = 1)
: fractional part of the fractional divider (M = 1)
Q
----------------------------------------------------------------------------- -
value and the divider divides by the P
=
=
1
223
557.5 kHz
-------------------------- -
2.5 kHz
P
1
=
+
f
-------------------------- - P
557.5 kHz
Mod
1
223
f
+
Mod
/ P
223 Q
1
+
–
–
--------- -
223
Q
1
1
1
Ref1
P
1
= 557.5 kHz), the accumulator content is incremented by the
=
P
1
1
times by (P
+
--------- -
223
Q
1
1
value. When the accumulator value reaches or
1
+ 1). Then, the accumulator holds the excess
1
+ 1) and (223 – Q
1
) times by P
4516D–CT0–10/05
1