AD6634BC/PCB Analog Devices Inc, AD6634BC/PCB Datasheet
AD6634BC/PCB
Specifications of AD6634BC/PCB
Related parts for AD6634BC/PCB
AD6634BC/PCB Summary of contents
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FEATURES 80 MSPS Wideband Inputs (14 Linear Bits Plus Three RSSI) Processes Two WCDMA Channels (UMTS or CDMA2000 Four GSM/EDGE, IS136 Channels Four Independent Digital Receivers in a Single Package Dual 16-Bit Parallel Output Ports Dual ...
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AD6634 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TABLE OF CONTENTS (continued) Memory Map for Output Port Control Registers . . . . . . . . . 45 0x08 Port A Control Register . . . . . . . . . . . . . . ...
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AD6634 GENERAL DESCRIPTION The AD6634 is a multimode 4-channel digital receive signal pro- cessor (RSP) capable of processing up to two WCDMA channels. Each channel consists of four cascaded signal processing elements: a frequency translator, two fixed coefficient decimating filters, ...
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SIGNAL OF INTEREST “IMAGE” – /2 –3 /8 –5 /16 – AFTER FREQUENCY TRANSLATION – /2 –3 /8 –5 /16 – FREQUENCY ...
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... Model Temperature Range AD6634BBC –40°C to +85°C (Ambient) AD6634BC/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6634 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter VDD VDDIO T AMBIENT ELECTRICAL CHARACTERISTICS Parameter (Conditions) LOGIC INPUTS (5 V Tolerant) Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Logic “1” Current (Inputs with Pull-Down) Logic “0” ...
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AD6634 GENERAL TIMING CHARACTERISTICS Parameter (Conditions) CLK TIMING REQUIREMENTS t CLK Period CLK t CLK Width Low CLKL t CLK Width High CLKH RESET TIMING REQUIREMENTS RESET Width Low t RESL INPUT WIDEBAND DATA TIMING REQUIREMENTS Input to ↑CLK Setup ...
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MICROPROCESSOR PORT TIMING CHARACTERISTICS Parameter (Conditions) MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM WRITE TIMING to ↑CLK Setup Time 3 t Control SC to ↑CLK Hold Time 3 t Control HC WR(RW) to RDY(DTACK) Hold Time t HWR ...
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AD6634 TIMING DIAGRAMS LIA–A LIA–B LIB–A LIB–B Figure 2. Level Indicator Output Switching Characteristics RESET SCLK SCLK SDI INx[13:0] EXPx[2:0] t CLK t CLKL CLK t CLKH t DLI t RESL Figure 3. RESET Timing Requirements t SCLKH t SCLKL ...
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SYNCA SYNCB SYNCC CYNCD CLK PCLK Figure 8. PCLK to CLK Switching Characteristics Divide by 1 CLK PCLK Figure 9. PCLK to CLK Switching Characteristics Divide PCLK PxACK Figure 10. Master Mode PxACK to PCLK ...
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AD6634 PCLK PxREQ t SPA PxACK Px[15:0] Figure 11. Master Mode PxACK to PCLK Switching Characteristics PCLK PxACK PxREQ Px[15:0] Figure 12. Master Mode PxREQ to PCLK Switching Characteristics PCLK PxACK Figure 13. Slave Mode PxACK to PCLK Setup and ...
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PCLK PxREQ t SPA PxACK Px[15:0] Figure 14. Slave Mode PxACK to PCLK Switching Characteristics PCLK PxACK PxREQ Px[15:0] Figure 15. Slave Mode PxREQ to PCLK Switching Characteristics PCLK LxCLKOUT Figure 16. LxCLKOUT to PCLK Switching Characteristics REV ...
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AD6634 LxCLKOUT WAIT > CYCLES ONE TIME CONNECTIVITY CHECK LxCLKIN Lx[7:0] Figure 17. LxCLKIN to LxCLKOUT Data Switching Characteristics LxCLKOUT Lx[7:0] t FDLCLKDAT Figure 18. LxCLKOUT to Lx[7:0] Data Switching Characteristics 8 LxCLKOUT CYCLES ...
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TIMING DIAGRAMS—INM MICROPORT MODE CLK RD (DS) WR (RW) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ACC FROM RDY ACC Figure 19. INM Microport Write Timing Requirements CLK RD (DS) WR ...
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AD6634 TIMING DIAGRAMS—MNM MICROPORT MODE CLK DS (RD) RW (WR) CS A[2:0] D[7:0] DTACK (RDY) NOTES t 1. ACC FROM THE FE OF DTACK ACC Figure 21. MNM Microport Write Timing Requirements CLK DS ...
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NO INB6 INB9 A CONNECT INB2 INB4 INB5 B INB0 INB3 INB7 C LIB-B INB1 D CLK IENB E EXPA1 EXPA0 EXPA2 F INA12 INA13 INA10 G INA11 INA9 INA7 H INA8 INA6 J INA5 INA4 K ...
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AD6634 Mnemonic POWER SUPPLY VDD VDDIO GND INPUTS 1 INA[13:0] 1 EXPA[2:0] 2 IENA 1 INB[13:0] 1 EXPB[2:0] 2 IENB RESET CLK PCLK LACLKIN LBCLKIN 1 SYNCA 1 SYNCB 1 SYNCC 1 SYNCD CS 1 CHIP_ID[3:0] CONTROL PAACK PAREQ PBACK ...
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EXAMPLE FILTER RESPONSE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –1000 –800 Figure 23. The Filter Above Is Based MSPS Input Data Rate and an Output Rate ...
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AD6634 INPUT DATA PORTS The AD6634 features dual high speed ADC input ports, input port A and input port B. The dual input ports allow for the most flexibility with a single tuner chip. These can be diversity inputs or ...
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Gain Switching The AD6634 includes circuitry that is useful in applications where either large dynamic ranges exist or where gain ranging convert- ers are employed. This circuitry allows digital thresholds to be set such that an upper and a lower ...
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AD6634 D11 (MSB AD6640 AD6634 D0 (LSB EXP 2 EXP 1 EXP 0 VDD Figure 28. Typical Interconnection of the AD6640 Fixed Point ADC and the AD6634 Scaling with Floating-Point or Gain-Ranging ...
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The NCO frequency value in registers 0x85 and 0x86 is interpreted as a 32-bit unsigned integer. The NCO frequency is calculated using the equation below. = × 32 NCO FREQ _ 2 MOD where, NCO_FREQ is the 32-bit integer (registers ...
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AD6634 Mode 10: Clock on IEN Transition to High In this mode, data is clocked into the chip only on the first clock edge after the rising transition of the IEN line. Although data is latched only on the first ...
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Table III. SSB rCIC2 Alias Rejection Table ( –50 dB rCIC2 rCIC2 2 1.79 3 1.508 4 1.217 5 1.006 6 0.853 7 0.739 8 0.651 9 0.581 10 0.525 11 0.478 12 0.439 13 0.406 14 0.378 ...
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AD6634 f ≤ CLK f SAMP The decimation ratio may be programmed from CIC5 (all integer values). The frequency response of the filter is given by the following equations. The gain and ...
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RAM COEFFICIENT FILTER The final signal processing stage is a sum-of-products decimat- ing filter with programmable coefficients. A simplified block diagram is shown in Figure 31. The data memories I-RAM and Q-RAM store the 160 most recent complex samples from ...
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AD6634 For RCF Scale of 0, Scaling Factor is equal to –18.06 dB, and for maximum RCF Scale of 15, Scaling Factor is equal to 72.25 dB. If Bit 7 is set, the same exponent will be used for both ...
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The AGC and the interpolation filters are not tied together and any one, or both of them, can be selected without the other. The AGC section can be bypassed, if desired, by setting Bit 0 of the AGC control word. ...
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AD6634 operation. The rms samples so obtained are subtracted from the request signal level, R, specified in registers (0x0B, 0x14), leaving an error term to be processed by the loop filter, G(z). The user sets this programmable request signal level, ...
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If averaging of four samples is used, the AGC will attack a sudden increase in signal level more slowly compared to no averaging. The same would apply to the manner in which the AGC would ...
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AD6634 5. The Channel BIST located at 0xA7 should be enabled by setting Bits 19–0 to the number of RCF outputs to observe. 6. Bit 4 of external address register 5 should be set high to start the soft sync. ...
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Set the Start on Pin Sync bit and the appropriate Sync Pin Enable high (Ext Address D). 5. When the Sync pin is sampled high by the AD6634 CLK, this enables the count ...
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AD6634 PCLK PxACK t DPREQ PxREQ t DPP I[15:0] Px[15:0] t DPIQ PxlQ t DPCH PxCH[1:0] PxCH[1:0] = CHANNEL # Figure 36. Channel Mode Interleaved Format PCLK PxACK t DPREQ PxREQ t DPP I[15:8]; Q[7:0] Px[15:0] t DPIQ PxlQ t ...
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PCLK PxACK t DPREQ PxREQ t DPP Px[15:0] I[15:0] Q[15:0] t DPIQ PxlQ t DPCH PxCH[0] = AGC# PxCH[1:0] PxCH[ Figure 39. AGC Output with RSSI Word Master/Slave PCLK Modes The parallel ports may operate in either Master ...
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AD6634 LINK PORT AGC AGC BYTES) (4 BYTES) ADDR 0x1B OR 0x1D BIT BIT BIT LINK PORT AGC ...
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Channel Address Register 00–7F Coefficient Memory (CMEM) 80 CHANNEL SLEEP 81 Soft_Sync Control Register 82 Pin_SYNC Control Register 83 Start Hold-Off Counter 84 NCO Frequency Hold-Off Counter 85 NCO Frequency Register 0 86 NCO Frequency Register 1 87 NCO Phase ...
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AD6634 Hold-Off Counter hits a value the Frequency Hold-Off Counter is set to 1, the register will be updated as soon as the shadow is written. 0x86: NCO Frequency Register 1 This register represents the 16 MSBs ...
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Channel Address Register 90 rCIC2 Decimation – rCIC2 Decimation – rCIC2 Scale 93 Reserved 94 CIC5 Decimation – CIC5 Scale 96 Reserved 97–9F Unused A0 RCF Decimation – RCF Decimation Phase A2 ...
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AD6634 Bits 9–5 are the actual scale value used when the Level Indicator, LI pin associated with this channel is active. Bits 4–0 are the actual scale value used when the Level Indicator, LI pin associated with this channel is ...
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Q output data through the microport. To accomplish this, the Map RCF data to BIST bit in the RCF Control register 2, 0xA9, should be set high. Sixteen bits of Q data can then be read through the microport ...
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AD6634 be dual-channel and determined by the state of the IENA pin. If the IENA pin is low, the input detection is directed to LIA-A. If the IENA pin is high, the input is directed to LIA-B. In either case, ...
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Table XV. Memory Map for Output Port Control Registers Channel Address Register 08 Port A Control Register 09 Port B Control Register 0A AGC A Control Register 0B AGC A Hold-Off Counter 0C AGC A Desired Level 0D AGC A ...
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AD6634 Table XV. Memory Map for Output Port Control Registers (continued) Channel Address Register 16 AGC B Loop Gain 17 AGC B Pole Location 18 AGC B Average Samples 19 AGC B Update Decimation 1A Parallel A Control 1B Link ...
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In order to access the Input/Output Port Registers, Bit 5 of SLEEP register (on external memory map) should be written high. The CAR is then written with the address to the correct Output Port Register. 0x08 Port A Control Register ...
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AD6634 set between 1 and 4 with bit representation 00 meaning one sample and bit representation 11 meaning four samples. 0x11 AGC A Update Decimation This 12-bit register sets the AGC decimation ratio from 1 to 4096. An appropriate scaling ...
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The channel output indicator pins can be used to determine which data came from which channel. Bit 5 determines the format of the output data-words. When Bit 5 = ...
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AD6634 MICROPORT CONTROL The AD6634 has an 8-bit microprocessor port and a serial control port. The use of each of these ports is described separately below. The interaction of the ports is then described. The microport interface is a multimode ...
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Table XVII. Microport Instructions Instruction Comment 0000 All chips and all channels will get the access. 0001 Channel all chips will get the access. 0010 Channel all chips will get the access. ...
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AD6634 address is set, External Address [0] DR0 must be the first data register read to initiate an internal access. DR2 is only four bits wide. Data written to the upper four bits of this register will be ignored. Likewise ...
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FRAME SCLK SDI Figure 47. Serial Word Structure and Serial Port Control Timing JTAG BOUNDARY SCAN The AD6634 supports a subset of IEEE Standard 1149.1 speci- fication. For additional details of the standard, please see “IEEE Standard ...
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AD6634 Internal Address = 0x087 */ // holding registers for NCO phase byte wide access data int d1, d0; // NCO frequency word (16-bits wide) NCO_PHASE = 0xCBEF; // write ACR write_micro(7, 0x03 ); // write CAR write_micro(6, 0x87); // ...