AD6650/PCB Analog Devices Inc, AD6650/PCB Datasheet - Page 36

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AD6650/PCB

Manufacturer Part Number
AD6650/PCB
Description
BOARD EVAL FOR AD6650 W/SOFTWARE
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6650/PCB

Rohs Status
RoHS non-compliant
Module/board Type
Evaluation Board
For Use With/related Products
AD6650
AD6650
Reg.
(Hex)
10
11
12
13
Mnemonic
AGC Control 4
AGC Control 5
Reserved
AGC Control 7
12 to 10: FD_Step
9 to 8: FA_Thresh
3 to 0: FA_Step
15 to 8: SPB Peak
Detector Period
7 to 0: Reserved
8 to 0: FD SPB Threshold
7 to 4: FA_Count
Bit
Width
13
3
2
4
4
16
8
8
7
Fast attack and fast decay loop parameters.
Fast decay step size.
Fast attack step size.
Slow loop peak detector period.
Fast decay signal plus blocker threshold.
Description
Fast attack threshold measured at the
antialiasing filters.
Fast attack count. The fast attack loop steps
the gain down by FA_Step for FA_Count
number of clock cycles.
Signal plus blocker peak detector period for
the slow loop; f
SPB peak period = ¼ × (f
Reserved.
Reserved.
Rev. A | Page 36 of 44
S
= 26 MHz; f
SAMP
SYM
/f
SYM
=270.833 kHz;
).
Additional Information
Code
0
1
2
.
.
6
7
Code
0
1
2
3
Code
0
1
2
.
.
14
15
Code
0
1
2
.
.
14
15
Code
0
1
2
.
.
254
255
Must be written 8’b00000000
Must be written 7’b0000000
Code
0
1
2
.
.
510
511
Step size (dB)
0 dB
0.094 dB
0.188 dB
.
.
0.564 dB
0.658 dB
Threshold
−6.02 dBFS
−3.1 dBFS
−0.915 dBFS
0 dBFS
Count
1
2
3
.
.
14
15
Step size (dB)
0 dB
0.094 dB
0.188 dB
.
.
1.316 dB
1.41 dB
Samples (f
clock cycles)
0
1
2
.
.
254
255
Threshold
0 dBFS
−0.094 dBFS
−0.188 dBFS
.
.
−47.94 dBFS
−48.034 dBFS
S

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