AD9861BCPZ-50 Analog Devices Inc, AD9861BCPZ-50 Datasheet - Page 8
![IC FRONT-END MIXED SGNL 64-LFCSP](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9861BCPZ-50
Manufacturer Part Number
AD9861BCPZ-50
Description
IC FRONT-END MIXED SGNL 64-LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9861-50EB.pdf
(52 pages)
Specifications of AD9861BCPZ-50
Rf Type
WLL, WLAN
Features
10-bit ADC(s), 10-bit DAC(s)
Package / Case
64-LFCSP
Supply Voltage Range
2.7V To 3.6V
Logic Case Style
LFCSP
No. Of Pins
64
Operating Temperature Range
-40°C To +85°C
Msl
MSL 3 - 168 Hours
Termination Type
SMD
Interface
SPI
No. Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9861BCPZ-50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9861
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5, 31
6, 32
7, 16, 50, 51, 61
8, 9
10, 13, 49, 53, 59
11
12
14, 15
17
18
19–28
29
30
33
Name
SPI_DIO
(Interp1)
SPI_CLK
(Interp0)
SPI_SDO/AUXSPI_SDO
(FD/HD)
ADC_LO_PWR/AUX_SPI_CS
DVDD
DVSS
AVDD
IOUT–A, IOUT+A
AGND, AVSS
REFIO
FSADJ
IOUT+B, IOUT−B
IFACE2
(10/20)
IFACE3
U9–U0
AUX1
AUX2
IFACE1
ADC_LO_PWR/AUX_SPI_CS
1
SPI_SDO/AUX_SPI_SDO
SPI_CLK
SPI_DIO
IOUT–A
IOUT+A
IOUT+B
IOUT–B
FSADJ
REFIO
AGND
AGND
DVDD
DVSS
AVDD
AVDD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Description
SPI: Serial Port Data Input.
No SPI: Tx Interpolation Pin, MSB.
SPI: Serial Port Shift Clock.
No SPI: Tx Interpolation Pin, LSB.
SPI: 4-Wire Serial Port Data Output/Data Output Pin for AuxSPI.
No SPI: Configures Full-Duplex or Half-Duplex Mode.
ADC Low Power Mode Enable. Defined at power-up. CS for AuxSPI.
Digital Supply.
Digital Ground.
Analog Supply.
DAC A Differential Output.
Analog Ground.
Tx DAC Band Gap Reference Decoupling Pin.
Tx DAC Full-Scale Adjust Pin.
DAC B Differential Output.
SPI: Buffered CLKIN. Can be configured as system clock output.
No SPI: For FD: Buffered CLKIN; For HD20 or HD10 : 10/20 Configuration Pin.
Clock Output.
Upper Data Bit 9 to Upper Data Bit 0.
Configurable as either AuxADC_A2 or AuxDAC_A.
Configurable as either AuxADC_A1 or AuxDAC_B.
SPI: For FD: TxSYNC; For HD20, HD10, or Clone: Tx/Rx.
No SPI: FD >> TxSYNC; HD20 or HD10: Tx/Rx.
Figure 3. Pin Configuration
Rev. 0 | Page 8 of 52
(Not to Scale)
AD9861
TOP VIEW
2, 3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CLKIN
AUXADC_REF
RESET
AUX_DACC/AUX_ADCB
L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
AUX_SPI_CLK
IFACE1
03606-0-019