AD607ARSZ-REEL Analog Devices Inc, AD607ARSZ-REEL Datasheet - Page 14

• Manufacturer Part Number: AD607ARSZ-REEL
• Description: IC RECEIVER IF SUBSYS LP 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD607ARSZ-REEL

• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Function: Receiver IF Subsystem
• Frequency: 500MHz
• Secondary Attributes: -8dBm Input Third Order Intercept
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Frequency Range: 400kHz To 12MHz
• Supply Voltage Range: 2.92V To 5.5V
• Rf Ic Case Style: SSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Operating Supply Voltage: 3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD607
TPC 19. Power Supply Current vs. Gain Control Voltage,
GREF = 1.5 V
TPC 18. Power-Up Response Time to PLL Stable
PRUP
RFLO
RFHI
VPS1
VPS2
10
15
5
0
TIMEBASE
MEMORY 1
TIMEBASE
MEMORY 2
TIMEBASE
DELTA T
START
TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV
40.2127ms
0.5
LOIP
GENERATOR
= 500 s/DIV
= 100.0mV/DIV
= 5.00 s/DIV
= 60.00mV/DIV
= 5.00 s/DIV
= 15.7990 s
= 40.2327ms
GENERATOR
BIAS
MIDPOINT
GAIN VOLTAGE – V
BIAS
1
40.2377ms
COM1 COM2
DELAY
OFFSET
DELAY
OFFSET
DELAY
STOP
VMID
MXOP
1.5
= 40.2377ms
= 154.0mV
= 40.2377ms
= 209.0mV
= 40.2377ms
= 40.2485ms
40.2627ms
BPF
2
Figure 13. Functional Block Diagram
IFLO
IFHI
2.5
–14–
PRODUCT OVERVIEW
The AD607 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or most of a double-conversion receiver, at input
frequencies up to 500 MHz, and an IF from 400 kHz to 12 MHz.
The internal I/Q demodulators and their associated phase-
locked loop, which can provide carrier recovery from the IF,
support a wide variety of modulation modes, including
n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V
is required (2.92 V minimum, 5.5 V maximum) at a typical
supply current of 8.5 mA at midgain. In the following discus-
sion, V
will be assumed to be 3 V.
Figure 13 shows the main sections of the AD607. It consists of a
variable gain UHF mixer and linear four-stage IF strip, which
together provide a voltage controlled gain range of more than
90 dB; dual demodulators, each comprising a multiplier fol-
lowed by a two-pole, 2 MHz low-pass filter; and a phase-locked
loop providing the inphase and quadrature clocks. A biasing
system with CMOS compatible power-down completes the
AD607.
Mixer
The UHF mixer is an improved Gilbert cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 500 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of ± 56 mV between RFHI and RFLO up to which the
mixer remains linear, and at the lower end by the noise level. It is
customary to define the linearity of a mixer in terms of the 1 dB
gain-compression point and third order intercept, which for the
AD607 are –15 dBm and –8 dBm, respectively, in a 50 Ω system.
VMID
VOLTAGE
P
PTAT
will be used to denote the power supply voltage, which
IFOP
BPF OR
LPF
AD607
DMIP
VQFO
IOUT
FDIN
FLTR
QOUT
GAIN
GREF
REV. C