LTC4402-1EMS8 Linear Technology, LTC4402-1EMS8 Datasheet - Page 6

• Manufacturer Part Number: LTC4402-1EMS8
• Description: IC CTRLR RF PWR MULTIBAND 8MSOP
• Manufacturer: Linear Technology

Specifications of LTC4402-1EMS8

• Rf Type: Cellular, GSM, GPRS, PCS, Wireless Modem, TDMA
• Frequency: 300MHz ~ 2.7GHz
• Features: Single Output
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC4402-1/LTC4402-2
This closes the RF power control loop and the RF power is
then controlled during ramp down.
LTC4402-1 Description
The LTC4402-1 is identical in performance to the
LTC4402-2 except that only one control output (V
available. The LTC4402-1 can drive a single band (300MHz
to 2400MHz) or a dual RF channel module with an
internal multiplexer. Several manufacturers offer dual RF
channel modules with an internal multiplexer.
General Layout Considerations
The LTC4402-X should be placed near the coupling com-
ponents. The feedback signal line to the RF pin should be
a 50 transmission line.
Capacitive Coupling
An alternative to a directional coupler is illustrated on the
first page of this data sheet. This method couples RF from
the power amplifier to the power controller through a
0.4pF 0.05pF capacitor and 50 series resistor, com-
pletely eliminating the directional coupler.
6
V
V
SHDN
T1: PART COMES OUT OF SHUTDOWN 11 s PRIOR TO BURST.
T2: INTERNAL TIMER COMPLETES AUTOZERO CORRECTION, TYPICALLY 9 s.
T3: BASEBAND CONTROLLER STARTS RF POWER RAMP UP AT LEAST 11 s AFTER
T4: BASEBAND CONTROLLER COMPLETES RAMP UP.
T5: CONTROL LOOP OPENS, V
T6: AM MODULATION STOPS, CONTROL LOOP CLOSES, V
T7: BASEBAND CONTROLLER STARTS RF POWER RAMP DOWN AT END OF BURST.
T8: RETURNS TO SHUTDOWN MODE BETWEEN BURSTS.
PCTL
PCA/B
HOLD
SHDN IS ASSERTED HIGH.
T1
11 s
T2 T3
2 s
LTC4402-X Timing Diagram
28 s
V
START
U
T4
PCA/B
T5
AM MODULATION PERIOD
INFORMATION
VOLTAGE HELD, AM MODULATION STARTS.
U
543 s
W
PCA/B
WILL FOLLOW DAC.
T6
T7
28 s
U
T8
PCA
4402 TD
) is
Application Note AN91 describes the capacitive coupling
scheme in full detail. Demo boards featuring this coupling
method are available upon request.
Power Ramp Profiles
The external voltage gain associated with the RF channel
can vary significantly between RF power amplifier types.
Frequency compensation generally defines the loop dy-
namics that impact the power/time response and possibly
(slow loops) the power ramp sidebands. The LTC4402-X
operates open loop until an RF voltage appears at the RF
pin, at which time the loop closes and the output power
follows the DAC profile. The RF power amplifier will
require a certain control voltage level (threshold) before an
RF output signal is produced. The LTC4402-X V
outputs must quickly rise to this threshold voltage in order
to meet the power/time profile. To reduce this time, the
LTC4402-X starts at 450mV. However, at very low power
levels the PCTL input signal is small, and the V
outputs may take several microseconds to reach the RF
power amplifier threshold voltage. To reduce this time, it
may be necessary to apply a positive pulse at the start of
the ramp to quickly bring the V
threshold voltage. This can generally be achieved with
DAC programming. The magnitude of the pulse is depen-
dent on the RF amplifier characteristics.
Power ramp sidebands and power/time are also a factor
when ramping to zero power. For RF amplifiers requiring
high control voltages, it may be necessary to further adjust
the DAC ramp profile. When the power is ramped down,
the loop will eventually open at power levels below the
LTC4402-X detector threshold. The LTC4402-X will then
go open loop and the output voltage at V
stop falling. If this voltage is high enough to produce RF
output power, the power/time or power ramp sidebands
may not meet specification. This problem can be avoided
by starting the DAC ramp from 200mV (Figure 1). At the
end of the cycle, the DAC can be ramped down to 0mV.
This applies a negative signal to the LTC4402-X thereby
ensuring that the V
200mV ramp step must be applied at least 2 s after SHDN
is asserted high to allow the autozero to cancel the step.
PCA/B
outputs will ramp to 0V. The
PCA/B
PCA
outputs to the
or V
PCB
PCA/B
PCA/B
will
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