SI4320-J1-FT Silicon Laboratories Inc, SI4320-J1-FT Datasheet - Page 17

• Manufacturer Part Number: SI4320-J1-FT
• Description: IC RCVR FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4320-J1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, OOK
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 315 MHz to 915 MHz
• Operating Supply Voltage: 2.2 V to 5.4 V
• Mounting Style: SMD/SMT
• Supply Current: 3 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1627-5

9. Data Rate Command
The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs.
BR = 10 MHz / 29 / (R+1) / (1 + cs*7)
In the receiver set R according the next function:
R= (10 MHz / 29 / (1 + cs*7)/ BR) – 1
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
BR is the bit rate set in the receiver and
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.

operate below this limit independently from process, temperature, or V
Supposing a maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the necessary relative accuracy is 0.68% in
slow mode and 2.1% in fast mode.
10. Output and FIFO Mode Command
Bit 4-7 <f3 : f0>:
Bit 2-3 <s1 : s0>:
Note:
BR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock recovery circuit will always
bit
bit
15
15
1
1
Clock recovery in slow mode:
VDI (Valid Data Indicator) see further details in Receiver Control Word, Synchron word in microcontroller mode is 2DD4h.
14
14
1
1
FIFO IT level. The FIFO generates IT when number of the received data bits reaches this level.
Set the input of the FIFO fill start condition:
13
13
0
s1
0
0
0
1
1
12
12
0
s0
0
0
1
0
1
11
11
VDI
Sync Word
Reserved
Always
1
1
FIFO fill start condition

10
10
0

1
BR/BR < 1/(29*N
BR is bit rate difference between the transmitter and the receiver. N
9
0
9
1
8
0
8
0
cs
bit
f3
7
7
)
r6
f2
6
6
dd
condition.
r5
f1
5
5
r4
f0
4
Clock recovery in fast mode:
4
s1
r3
3
3
s0
r2
2
2
r1
1
1
ff
r0
fe
0
0

BR/BR<3/(29*N
bit
is the maximal number of
CE85h
C823h
POR
POR
bit
Si4320
)
17