STA8058TR STMicroelectronics, STA8058TR Datasheet - Page 4

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STA8058TR

Manufacturer Part Number
STA8058TR
Description
MOD TESEO MCM STA2058 104LFBGA
Manufacturer
STMicroelectronics
Series
TESEO™r
Datasheet

Specifications of STA8058TR

Sensitivity
-159dBm
Applications
GPS
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 64kB RAM
Antenna Connector
PCB, Surface Mount
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
104-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Frequency
-
Data Rate - Maximum
-
Modulation Or Protocol
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Features summary
4/14
Two I
I
one SPI, so either 2 x SPI + 1 x I
Enhanced interrupt controller supports 32 interrupt vectors, independently maskable,
with interrupt vector table for faster response and 16 priority levels, software
programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ.
Wake-up unit allows exiting from powerdown modes by detection of an event on two
external pins (one is active high and other is active low) or on internal Real Time Clock
alarm.
USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume
support
High level data link controller (HDLC) unit supports full duplex operating mode, NRZ,
NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator.
RF front-end features:
2
C mode (400 KHz), 7/10 bit addressing modes. One I
LOW IF (4 MHz) architecture
Compatible with GPS L1 signal
VGA gain internally regulated
On chip programmable PLL
SPI interface
2
C interfaces provide multi-master and slave functions, support normal and fast
2
C or 1 x SPI + 2 x I
2
C may be used at a time.
2
C Interface is multiplexed with
STA8058

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