SI4703-B17-GMR Silicon Laboratories Inc, SI4703-B17-GMR Datasheet - Page 17

• Manufacturer Part Number: SI4703-B17-GMR
• Description: IC TUNER FM RADIO RDS/RBDS 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4703-B17-GMR

• Frequency: 76MHz ~ 108MHz
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: *
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: *
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

4.8.2. 2-wire Control Interface
For two-wire operation, a transfer begins with the
START condition. The control word is latched internally
on rising SCLK edges and is eight bits in length,
comprised of a seven bit device address equal to
0010000b and a read/write bit (write = 0 and read = 1).
The device acknowledges the address by setting SDIO
low on the next falling SCLK edge.
For write operations, the device acknowledge is
followed by an eight bit data word latched internally on
rising edges of SCLK. The device always acknowledges
the data by setting SDIO low on the next falling SCLK
edge. An internal address counter automatically
increments to allow continuous data byte writes, starting
with the upper byte of register 02h, followed by the
lower byte of register 02h, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous writes cease. Data transfer ceases with the
STOP command. After every STOP command, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC should return an acknowledge if an
additional byte of data will be requested. Data transfer
ceases with the STOP command. After every STOP
command, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to Table 6, “2-Wire Control Interface Characteristics
on page 8, Figure 5, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 9 and Figure 6,
“2-Wire Control Interface Read and Write Timing
Diagram,” on page 9.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4703 and its
control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
one of two methods may be used to select between
2-wire and 3-wire control interface operation.
Busmode select method 1 requires the use of the
GPIO3, SEN, and SDIO pins. The GPIO3 pin should be
Confidential Rev. 1.0
1
,”
externally driven low, set to hi-Z or left floating, and the
SDIO pin should be externally driven low on the rising
edge of RST. The GPIO3 pin has an internal 1 M
pulldown resistor to ensure proper bus mode selection.
To select 2-wire operation of the control interface, the
SEN pin should be externally driven high on the rising
edge of RST. To select 3-wire operation of the control
interface, the SEN pin should be externally driven low
on the rising edge of RST. Refer to Table 4, “Reset
Timing Characteristics,” on page 6 and Figure 1, “Reset
Timing Parameters for Busmode Select Method 1,” on
page 6.
Busmode select method 2 only requires the use of the
GPIO3 and GPIO1 pins. The GPIO3 pin should be
driven high on the rising edge of RST. Using this control
interface bus selection method, a 100 k or lower
pull-up resistor should be used on the GPIO3 pin. To
select 2-wire operation of the control interface, the
GPIO1 and GPIO3 pins should be externally driven high
on the rising edge of RST. To select 3-wire operation of
the control interface, the GPIO1 pin should be externally
driven low on the rising edge of RST. Refer to Table 4,
“Reset Timing Characteristics,” on page 6 and Figure 2,
“Reset Timing Parameters for Busmode Select Method
2,” on page 6. Table 8 below summarizes the two bus
selection methods.
Select Method
Notes:
Xtal Oscillator
Xtal Oscillator
Xtal Oscillator
Xtal Oscillator
Busmode
Table 8. Selecting 2-Wire or 3-Wire Control
1. All parameters applied on rising edge of RST.
2. GPIO3 is internally pulled down with a 1 M resistor.
3. GPIO3 should be externally driven low, set to high-Z
4. GPIO3 should be left floating.
5. GPIO3 should be externally driven high (100 kor
(10 M or greater pull-up) or float.
smaller pull-up).
1
1
1
1
2
2
2
2
Interface Busmode Operation
SEN SDIO GPIO1 GPIO3
NA
NA
X
X
0
1
0
1
NA
NA
X
X
0
0
0
0
Si4703-B17
NA
NA
X
X
X
X
0
1
NA
NA
0
0
0
0
1
1
3
3
4
4
5
5
2
1
mode
3-wire
2-wire
3-wire
2-wire
3-wire
2-wire
Bus
NA
NA
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