MICRF022BM-FS48 Micrel Inc, MICRF022BM-FS48 Datasheet - Page 12
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MICRF022BM-FS48
Manufacturer Part Number
MICRF022BM-FS48
Description
IC RECEIVER ASK 300-440MHZ 8SOIC
Manufacturer
Micrel Inc
Datasheet
1.MICRF002YM.pdf
(17 pages)
Specifications of MICRF022BM-FS48
Frequency
300MHz ~ 440MHz
Sensitivity
-97dBm
Data Rate - Maximum
10 kbps
Modulation Or Protocol
ASK, OOK
Applications
RKE
Current - Receiving
2.2mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
4.75 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Memory Size
-
Power Supply Bypass Capacitors
V
the IC pins. Supply bypass capacitors are strongly
recommended. They should be connected to V
V
For best performance, connect V
supply only (that is, keep V
through the V
Increasing Selectivity with an Optional BandPass
Filter
For
environments, a fixed value band-pass network may be
connected between the ANT pin and V
additional receive selectivity and input overload protection.
A minimum input configuration is included in Figure 7 it
provides some filtering and necessary overload protection.
Data Squelching
During quiet periods (no signal) the data output (DO pin)
transitions randomly with noise. Most decoders can
discriminate between this random noise and actual data but
for some system it does present a problem. There are three
possible approaches to reducing this output noise:
The simplest solution is add analog squelch by introducing
a small offset, or squelch voltage, on the C
noise does not trigger the internal comparator. Usually
20mV to 30mV is sufficient, and may be achieved by
connecting a several-megohm resistor from the C
either V
Since the MICRF002 has receiver AGC noise at the
internal comparator input is always the same, set by the
AGC. The squelch offset requirement does not change as
the local noise strength changes from installation to
installation. Introducing squelch will reduce sensitivity and
also reduce range. Only introduce an amount of offset
sufficient to quiet the output. Typical squelch resistor values
range from 6.8MΩ to 10MΩ.
Wake-Up Function
The WAKEB output signal can be used to reduce system
power consumption by enabling the rest of a system when
an RF signal is present. The WAKEB is an output logic
signal which goes active low when the IC detects a
constant RF carrier. The wake-up function is unavailable
when the IC is in shutdown mode.
To activate the Wake-Up function, a received constant RF
carrier must be present for 128 counts or the internal
system clock. The internal system clock is derived from the
Micrel, Inc.
July 2008
DDBB
DDRF
1. Analog squelch to raise the demodulator threshold
2. Digital squelch to disable the output when data is
3. Output filter to filter the (high frequency) noise
applications
and should have the shortest possible lead lengths.
and V
SS
not present
glitches on the data output pin.
or V
DDRF
SSRF
DD
, depending on the desired offset polarity.
should be connected together directly at
return path).
located
in
SSBB
SSRF
high
currents from flowing
to V
SSBB
ambient
SSRF
TH
at the power
pin so that
to provide
DDBB
TH
pin to
noise
and
12
reference oscillator and is 1/256 the reference oscillator
frequency. For example:
where:
The Wake-Up counter will reset immediately after a
detected RF carrier drops. The duration of the Wake-Up
signal output is then determined by the required wake up
time plus an additional RF carrier on time interval to create
a wake up pulse output.
For designers who wish to use the wakeup function while
squelching the output, a positive squelching offset voltage
must be used. This simply requires that the squelch resistor
be connected to a voltage more positive than the quiescent
voltage on the C
absence of a transmission.
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF002
are diagrammed in Figures 1 through 6. The ESD
protection diodes at all input and output pins are not shown.
C
Figure 2 illustrates the C
is driven from a P-channel MOSFET source-follower with
approximately 10µA of bias. Transmission gates TG1 and
TG2 isolate the 6.9pF capacitor. Internal control signals
PHI1/PHI2 are related in a manner such that the
impedance across the transmission gates looks like a
“resistance” of approximately 100kΩ. The dc potential at
the C
TH
Pin
TH
Demodulator
pin is approximately 1.6V
f
f
P
128 counts x 0.04ms = 5.12ms
f
f
P
WAKEB Output Pulse Time = T
RF Carrier On Time
T
S
T
S
S
S
2.85Vdc
= 6.4MHz
= f
= reference oscillator frequency
= system clock frequency
= 1/f
= system clock period
Signal
T
/256 = 25kHz
S
= 0.04ms
TH
VDDBB
VSSBB
Figure 2. CTH Pin
pin so that the data output is low in
TH
PHI2B
PHI2
pin interface circuit. The C
VSSBB
MICRF002/RF022
PHI1B
PHI1
WAKE
M9999-070808
+ Additional
CTH
TH
pin