CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet - Page 15
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CYWUSB6935-48LFXC
Manufacturer Part Number
CYWUSB6935-48LFXC
Description
IC USB WIRELESS 2.4GHZ 48VQFN
Manufacturer
Cypress Semiconductor Corp
Specifications of CYWUSB6935-48LFXC
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Transmitting Current
69.1mA
Data Rate
62.5Kbps
Frequency Range
2.4GHz To 2.483GHz
Modulation Type
GFSK
Rf Ic Case Style
QFN
No. Of Pins
48
Supply Voltage Range
2.7V To 3.6V
Operating
RoHS Compliant
Sensitivity Dbm
-95dBm
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1625
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6935-48LFXC
Manufacturer:
MICRON
Quantity:
1 001
Part Number:
CYWUSB6935-48LFXC
Manufacturer:
CIRRUS
Quantity:
20 000
Document 38-16008 Rev. *A
Bit
7:4
3
2
1
0
Bit Name
7:4 Reserved
3
2
1
0
Note:
4.
Addr: 0x0D
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling
IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in
transmit mode. These registers are read-only.
Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register
Overflow
Done
Empty
Name
Reserved
Underflow
Overflow
Done
Empty
7
7
Addr: 0x0E
Description
These bits are reserved. This register is read-only.
(Reg 0x0F) has occurred.
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs
when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register
(Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the
Transmit Interrupt Status register (Reg 0x0E).
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)
has occurred.
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs
when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.
This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Done bit is used to signal the end of a data transmission.
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only
assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status
register (Reg 0x0E)
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES
Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when
the data is loaded into the transmitter, and it is ok to write new data.
Description
These bits are reserved and should be written with zeroes.
The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit
SERDES Data register (Reg 0x0F)
An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does
not have any data.
The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data
register (0x0F).
An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F)
before the preceding data has been transferred to the transmit shift register.
The Done bit is used to enable the interrupt that signals the end of the transmission of data.
The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and
there is no more data for it to transmit.
The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty.
The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer
and it's safe to load the next byte
1 = Underflow Interrupt pending
0 = No Underflow Interrupt pending
1 = Overflow Interrupt pending
0 = No Overflow Interrupt pending
1 = Done Interrupt pending
0 = No Done Interrupt pending
1 = Empty Interrupt pending
0 = No Empty Interrupt pending
1 = Underflow interrupt enabled
0 = Underflow interrupt disabled
1 = Overflow interrupt enabled
0 = Overflow interrupt disabled
1 = Done interrupt enabled
0 = Done interrupt disabled
1 = Empty interrupt enabled
0 = Empty interrupt disabled
6
6
Reserved
Reserved
Figure 7-15. Transmit SERDES Interrupt Status
Figure 7-14. Transmit SERDES Interrupt Enable
5
5
REG_TX_INT_STAT
REG_TX_INT_EN
4
4
Underflow
Underflow
3
3
Overflow
Overflow
2
2
[4]
Done
Done
1
1
CYWUSB6935
Default: 0x00
Default: 0x00
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