EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 158
![MODULE EM357 PA/LNA W/ANT TG](/photos/14/20/142080/em357-mod-lr-ant-tg_sml.jpg)
EM357-MOD-LR-ANT-TG
Manufacturer Part Number
EM357-MOD-LR-ANT-TG
Description
MODULE EM357 PA/LNA W/ANT TG
Manufacturer
Ember
Specifications of EM357-MOD-LR-ANT-TG
Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
25mA
Current - Transmitting
42mA
Data Interface
PCB, Surface Mount
Memory Size
192kB Flash, 12kB RAM
Antenna Connector
On-Board, Chip
Operating Temperature
-40°C ~ 85°C
Package / Case
Module
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Applications
-
Sensitivity
-
Other names
636-1020
- Current page: 158 of 245
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TIMx_SMCR
TIM1_SMCR
Timer 1 Slave Mode Control Register
TIM2_SMCR
Timer 2 Slave Mode Control Register
Bitname
TIM_ETP
TIM_ECE
TIM_ETPS
TIM_MSM
TIM_ETP
31
23
15
7
0
0
TIM_ECE
30
22
14
0
0
6
Bitfield
[13:12]
[15]
[14]
TIM_TS
29
21
13
0
0
5
Access
RW
RW
RW
TIM_ETPS
Description
External Trigger Polarity.
This bit selects whether ETR or the inverse of ETR is used for trigger operations.
0: ETR is non-inverted, active at a high level or rising edge.
1: ETR is inverted, active at a low level or falling edge.
External Clock Enable.
This bit enables external clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note 1: Setting the TIM_ECE bit has the same effect as selecting external clock mode 1
with TRGI connected to ETRF (TIM_SMS=111 and TIM_TS=111).
Note 2: It is possible to use this mode simultaneously with the following slave modes:
reset mode, gated mode and trigger mode. TRGI must not be connected to ETRF in this
case (the TIM_TS bits must not be 111).
Note 3: If external clock mode 1 and external clock mode 2 are enabled at the same
time, the external clock input will be ETRF.
External Trigger Prescaler.
External trigger signal ETRP frequency must be at most 1/4 of CK frequency. A prescaler
can be enabled to reduce ETRP frequency. It is useful with fast external clocks.
00: ETRP prescaler off.
01: Divide ETRP frequency by 2.
10: Divide ETRP frequency by 4.
11: Divide ETRP frequency by 8.
28
20
12
4
0
0
Final
9-34
27
19
11
0
0
3
0
26
18
10
2
0
0
Address: 0x4000F008 Reset: 0x0
Address: 0x4000E008 Reset: 0x0
TIM_ETF
TIM_SMS
25
17
0
0
9
1
120-035X-000G
24
16
0
0
8
0
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