SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 188

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
18.2. Power-Fail (VDD_MCU/DC+ Supply Monitor) Reset
Si1010/1/2/3/4/5 devices have a VDD_MCU/DC+ Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes VDD_MCU/DC+ to drop below V
pin to be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD_MCU/DC+
returns to a level above V
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD_MCU/DC+
supply monitor is enabled and selected as a reset source. The enable state of the VDD_MCU/DC+ supply
monitor and its selection as a reset source is only altered by power-on and power-fail resets. For example,
if the VDD_MCU/DC+ supply monitor is de-selected as a reset source and disabled by software, then a
software reset is performed, the VDD_MCU/DC+ supply monitor will remain disabled and de-selected after
the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
above V
source select state of the VDD_MCU/DC+ supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD_MCU/DC+ supply falls below the V
ate an interrupt. See Section “12. Interrupt Handler” on page 134 for more details.
Important Note: To protect the integrity of Flash contents, the VDD_MCU/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD_MCU/DC+ supply monitor is not enabled, any erase or write performed on Flash
memory will cause a Flash Error device reset.
188
POR
while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset
VBAT
VDD
V
V
WARN
POR
RST
WARN
VDDOK
SLEEP
RST
RST
Figure 18.3. Power-Fail Reset Timing Diagram
Power-Fail Reset
, the CIP-51 will be released from the reset state.
Active Mode
POR
. A large capacitor can be used to hold the power supply voltage
VDD/DC+
VBAT
WARN
Rev. 1.0
threshold. The VDDOK bit can be configured to gener-
RAM Retained - No Reset
Sleep Mode
Note: Wakeup signal
required after new
battery insertion
RST
will cause the RST
t