SI1010-A-GM Silicon Laboratories Inc, SI1010-A-GM Datasheet
SI1010-A-GM
Specifications of SI1010-A-GM
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SI1010-A-GM Summary of contents
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... Complete development kit High-Speed 8051 µC Core Pipelined instruction architecture; executes 70% of instruc- - tions system clocks MIPS throughput with 25 MHz clock - - Expanded interrupt handler Memory - 768 bytes RAM 16 kB (Si1010/2/ (Si1011/3/5) Flash; In-system programmable ANALOG PERIPHERALS 12/10-bit A 75/300 ksps VREF TEMP ...
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... Si1010/1/2/3/4/5 Table of Contents 1. System Overview ..................................................................................................... 20 1.1. Typical Connection Diagram ............................................................................. 24 1.2. CIP-51™ Microcontroller Core .......................................................................... 25 1.2.1. Fully 8051 Compatible .............................................................................. 25 1.2.2. Improved Throughput................................................................................ 25 1.2.3. Additional Features ................................................................................... 25 1.3. Port Input/Output ............................................................................................... 26 1.4. Serial Ports ........................................................................................................ 27 1.5. Programmable Counter Array............................................................................ 27 1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode ...
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... Programming the Flash Memory ................................................................... 146 13.1.1. Flash Lock and Key Functions .............................................................. 146 13.1.2. Flash Erase Procedure ......................................................................... 147 13.1.3. Flash Write Procedure .......................................................................... 147 13.2. Non-Volatile Data Storage............................................................................. 147 13.3. Security Options ............................................................................................ 148 13.4. Determining the Device Part Number at Run Time ....................................... 150 Si1010/1/2/3/4/5 Rev. 1.0 3 ...
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... Si1010/1/2/3/4/5 13.5. Flash Write and Erase Guidelines ................................................................. 151 13.5.1. VDD Maintenance and the VDD Monitor .............................................. 151 13.5.2. PSWE Maintenance .............................................................................. 151 13.5.3. System Clock ........................................................................................ 152 13.6. Minimizing Flash Read Current ..................................................................... 153 14. Power Management ............................................................................................. 157 14.1. Normal Mode ................................................................................................. 158 14.2. Idle Mode....................................................................................................... 158 14 ...
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... Assigning Port I/O Pins to Digital Functions.......................................... 222 21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 222 21.3. Priority Crossbar Decoder ............................................................................. 223 21.4. Port Match ..................................................................................................... 228 21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 231 Si1010/1/2/3/4/5 Rev. 1.0 5 ...
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... Si1010/1/2/3/4/5 22. EZRadioPRO Serial Interface (SPI1)................................................................... 239 22.1. Signal Descriptions........................................................................................ 240 22.1.1. Master Out, Slave In (MOSI)................................................................. 240 22.1.2. Master In, Slave Out (MISO)................................................................. 240 22.1.3. Serial Clock (SCK) ................................................................................ 240 22.1.4. Slave Select (NSS) ............................................................................... 240 22.2. SPI Master Operation on the MCU Core Side............................................... 240 22 ...
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... Hardware Slave Address Recognition .................................................. 306 24.4.4. Data Register ........................................................................................ 309 24.5. SMBus Transfer Modes................................................................................. 309 24.5.1. Write Sequence (Master) ...................................................................... 309 24.5.2. Read Sequence (Master) ...................................................................... 310 24.5.3. Write Sequence (Slave) ........................................................................ 311 24.5.4. Read Sequence (Slave) ........................................................................ 312 24.6. SMBus Status Decoding................................................................................ 313 Si1010/1/2/3/4/5 Rev. 1.0 7 ...
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... Si1010/1/2/3/4/5 25. UART0 ................................................................................................................... 318 25.1. Enhanced Baud Rate Generation.................................................................. 319 25.2. Operational Modes ........................................................................................ 319 25.2.1. 8-Bit UART ............................................................................................ 320 25.2.2. 9-Bit UART ............................................................................................ 320 25.3. Multiprocessor Communications ................................................................... 321 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 325 26.1. Signal Descriptions........................................................................................ 326 26.1.1. Master Out, Slave In (MOSI)................................................................. 326 26 ...
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... Register Descriptions for PCA0..................................................................... 373 29. C2 Interface .......................................................................................................... 379 29.1. C2 Interface Registers................................................................................... 379 29.2. C2 Pin Sharing .............................................................................................. 382 Document Change List.............................................................................................. 383 Contact Information................................................................................................... 384 Si1010/1/2/3/4/5 Rev. 1.0 9 ...
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... Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 29 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 30 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 30 Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) .............................................. 36 Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 37 Figure 3.3. QFN-42 Package Drawing .................................................................... 38 Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 40 Figure 3 ...
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... Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111 Figure 8.1. CIP-51 Block Diagram ......................................................................... 114 Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123 Figure 9.2. Flash Program Memory Map ............................................................... 124 Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices) .................... 148 Figure 14.1. Si1010/1/2/3/4/5 Power Distribution .................................................. 158 Figure 15 ...
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... Si1010/1/2/3/4/5 Figure 23.18. Manchester Coding Example .......................................................... 276 Figure 23.19. Header ............................................................................................. 278 Figure 23.20. POR Glitch Parameters ................................................................... 279 Figure 23.21. General Purpose ADC Architecture ................................................ 282 Figure 23.22. Temperature Ranges using ADC8 .................................................. 284 Figure 23.23. WUT Interrupt and WUT Operation ................................................. 287 Figure 23.24. Low Duty Cycle Mode ..................................................................... 288 Figure 23.25. RSSI Value vs. Input Power ............................................................ 290 Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design— ...
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... Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 368 Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 369 Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 370 Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 371 Figure 29.1. Typical C2 Pin Sharing ...................................................................... 382 Si1010/1/2/3/4/5 Rev. 1.0 13 ...
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... Si1010/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 31 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 .................................................. 32 Table 3.2. QFN-42 Package Dimensions ................................................................ 39 Table 3.3. PCB Land Pattern ................................................................................... 43 Table 4.1. Absolute Maximum Ratings .................................................................... 44 Table 4.2. Global Electrical Characteristics ............................................................. 45 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 55 Table 4 ...
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... Table 26.1. SPI Slave Timing Parameters ............................................................ 337 Table 27.1. Timer 0 Running Modes ..................................................................... 340 Table 28.1. PCA Timebase Input Options ............................................................. 361 Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules ................................................................ 364 Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 372 Si1010/1/2/3/4/5 Rev. 1.0 15 ...
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... Si1010/1/2/3/4/5 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 85 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 86 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 87 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 88 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 89 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 90 SFR Definition 5 ...
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... SFR Definition 21.13. P1: Port1 .................................................................................. 235 SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 235 SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 236 SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 236 SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 237 SFR Definition 21.18. P2: Port2 .................................................................................. 237 Si1010/1/2/3/4/5 Rev. 1.0 17 ...
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... Si1010/1/2/3/4/5 SFR Definition 21.19. P2MDOUT: Port2 Output Mode ............................................... 238 SFR Definition 21.20. P2DRV: Port2 Drive Strength .................................................. 238 SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 244 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 245 SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 246 SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 247 SFR Definition 24 ...
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... C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 381 C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 381 Si1010/1/2/3/4/5 Rev. 1.0 19 ...
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... The Port I/O and RST pins are tolerant of input signals The Si1010/1/2/3/4/5 devices are available in a 42-pin QFN package which is lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.4. ...
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... MHz Oscillator External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.1. Si1010 Block Diagram CIP-51 8051 Power On Controller Core Reset/PMU 8k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 512 Byte XRAM ...
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... Si1010/1/2/3/4/5 CIP-51 8051 Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 512 Byte XRAM Hardware C2D VDD VREG GND Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External XTAL1 Oscillator XTAL2 ...
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... VBAT Low Power Converter 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.6. Si1015 Block Diagram Si1010/1/2/3/4/5 Analog Peripherals 6-bit IREF0 IREF External Internal VREF VREF VDD VREF A 12/10-bit Temp M 75/300 ksps Sensor U ...
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... Figure 1.7. Si1012/3 RX/TX Direct-Tie Application Example Supply Voltage C6 100 p TR & ANT-DIV L3 Switch Figure 1.8. Si1010/1 Antenna Diversity Application Example 30MHz 1u L1 VDD_RF VDD_M CU VDD_DIG TX Px.x C1 RFp Si101x RXn Programm able load capacitors for X1 are integrated. L1-L6 and C1-C5 values depend on frequency band , antenna im pedance, output power and supply voltage range ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.2.3. Additional Features The Si1010/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous ana- log and digital peripherals to interrupt the controller ...
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... Si1010/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 12 I/O pins. Port pins are organized as three byte-wide ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources ...
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... Serial Ports The Si1010/1/2/3/4/5 Family includes an SMBus/I rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hard- ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.5. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers ...
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... SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1010/1/2/3/4/5 devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autono- mous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention ...
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... Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). ...
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... Si1010/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 + Px.x Px.x CP1 - Px.x Figure 1 ...
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... Ordering Information Table 2.1. Product Selection Guide Si1010-A- 768 P Si1011-A- 768 P Si1012-A- 768 P Si1013-A- 768 P Si1014-A- 768 P Si1015-A- 768 P *The ‘F9xx Plus features are a set of enhancements that allow greater power efficiency and increased functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO, VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The ‘ ...
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... Si1010/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 Name Pin Number Si1010/1 Si1014/5 Si1012/3 VDD_MCU 38 — GND_MCU 37 — — VBAT 41 GND — 38 VBAT- DCEN — 40 VDD_MCU / — 39 DC+ GND_MCU — 37 DC– VDD_RF 16 16 VDD_DIG 28 28 VR_DIG ...
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... Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Type Si1010/1 Si1014/5 Si1012/3 RST I/O C2CK D I/O P2. I/O C2D D I/O XTAL3 XTAL4 Out P0 I REF A Out P0 I AGND P0 I XTAL1 P0 I Out XTAL2 Si1010/1/2/3/4/5 Description Device Reset. Open-drain output of internal POR or V monitor. An external source can initiate a system reset by driving this pin low for at least 15 µ ...
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... Si1010/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Si1010/1 Si1014/5 Si1012 CNVSTR P0 IREF0 GPIO_0 24 24 GPIO_1 25 25 GPIO_2 26 26 nIRQ 11 11 XOUT 12 12 XIN Type Description D I/O or Port 0.4. See Port I/O section for a complete description. ...
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... Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Type Si1010/1 Si1014/5 Si1012/3 NC 14, 20, 14, 20 SDN RXp RXn ANT_A Si1010/1/2/3/4/5 Description No Connect. May be left floating or tied to power or ground. EZRadioPRO peripheral shutdown pin. When driven to logic HIGH, the EZRadioPRO peripheral will be completely shut down and the contents of the EZRadioPRO registers will be lost ...
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... Si1010/1/2/3/4/5 XTAL3 1 N.C. 2 N.C. 3 P1.6 4 P1.5 5 P1.4 6 N.C. 7 N.C. 8 N.C. 9 N.C. 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) 36 GND_M CU Si1010/1/2/3 Top View GND_RF Rev. 1.0 35 P0.1/AGND 34 P0.2/XTAL1 33 P0.3/XTAL2 32 P0.4/TX 31 P0.5/RX 30 P0.6/CNVSTR P0.7/IREF0 29 VDD_DIG 28 VR_DIG 27 26 GPIO_2 25 GPIO_1 ...
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... XTAL4 2 XTAL3 3 P1.6 4 P1.5 5 P1.4 6 N.C. 7 N.C. 8 N.C. 9 N.C. 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.2. Si1004/5 Pinout Diagram (Top View) Si1010/1/2/3/4/5 GND_M CU Si1014/5 Top View GND_RF Rev. 1.0 35 P0.1/AGND 34 P0.2/XTAL1 P0.3/XTAL2 33 P0.4/TX 32 P0.5/RX 31 P0.6/CNVSTR 30 29 P0.7/IREF0 28 VDD_DIG 27 VR_DIG GPIO_2 26 25 GPIO_1 ...
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... Si1010/1/2/3/4/5 Figure 3.3. QFN-42 Package Drawing 38 Rev. 1.0 ...
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... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. All pitches other than P1, P2 are represented by e. Si1010/1/2/3/4/5 Dimension Min Typ F 0.07 REF G 1 ...
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... Si1010/1/2/3/4/5 Figure 3.4. Typical QFN-42 Landing Diagram 40 Rev. 1.0 ...
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... Figure 3.5. VIA Placement and Keepout Region Si1010/1/2/3/4/5 Rev. 1.0 41 ...
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... Si1010/1/2/3/4/5 Figure 3.6. Typical PCB Stencil Diagram 42 Rev. 1.0 ...
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... A 3x3 array of 0.8 mm square openings on 1.0 mm pitch should be used for the lower center ground pad. 5. Card Assembly A No-Clean, Type-3 solder paste is recommended. 1. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 2. Table 3.3. PCB Land Pattern Rev. 1.0 Si1010/1/2/3/4/5 Value 4.75 0.95 0.30 7.00 0.30 0.70 0.50 > ...
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... This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 44 ” refers to the VDD_MCU supply voltage on Si1010/1/2/3 devices and ” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifica- Conditions Min – ...
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... Minimum RAM Data VDD (not in Sleep Mode) 1 Retention Voltage VBAT (in Sleep Mode) 2 SYSCLK (System Clock) T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specified Operating Temperature Range Si1010/1/2/3/4/5 Conditions Min 0.9 1.8 1.8 1.8 — — –40 Rev. 1.0 Typ ...
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... Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode ...
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... LFO) VBAT Supply Monitor) Digital Supply Current 1 °C (Sleep Mode) 3 °C 3 °C 1 °C 3 °C 3 °C (includes VBAT supply monitor) Digital Supply Current 1 °C (Sleep Mode, VBAT Supply Monitor Disabled) Si1010/1/2/3/4/5 Conditions Min — C — ° C — ° C — ° C — ...
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... Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode ...
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... Figure 4.1. Active Mode Current (External CMOS Clock) Si1010/1/2/3/4/5 F > 14 MHz Oneshot Bypassed 185 uA/MHz Frequency (MHz) Rev. 1.0 < 160 uA/MHz 49 ...
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... Si1010/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 ...
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... Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC Si1010/1/2/3/4/5 Load Current (mA) Rev. 1.0 51 ...
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... Si1010/1/2/3/4/5 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC Rev. 1.0 ...
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... Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC Si1010/1/2/3/4/5 Load current (mA) Rev. 1.0 53 ...
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... Si1010/1/2/3/4/5 Figure 4.6. Typical One-Cell Suspend Mode Current 54 Rev. 1.0 ...
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... V – 0.6 DD 0.7 x VDD — — — 1.8 V — 3.6 V — DD Rev. 1.0 Si1010/1/2/3/4/5 Typ Max Units V — — — — See Chart — — — — See Chart — V — 0.6 — 0.1 See Chart — ...
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... Si1010/1/2/3/4/5 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.7. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode Load Current (mA) Typical VOH (Low Drive Mode Load Current (mA) Rev. 1.0 VDD = 3.6V VDD = 3 ...
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... Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Load Current (mA) Figure 4.8. Typical VOH Curves, 0.9–1.8 V Rev. 1.0 Si1010/1/2/3/4/5 VDD = 1.8V VDD = 1.5V VDD = 1.2V VDD = 0. VDD = 1.8V VDD = 1.5V VDD = 1.2V VDD = 0. ...
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... Si1010/1/2/3/4/5 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.9. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V -60 -50 -40 -30 -20 -10 Load Current (mA) Typical VOL (Low Drive Mode) VDD = 3 ...
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... VDD = 1.8V 0.4 VDD = 1.5V VDD = 1.2V 0.3 VDD = 0.9V 0.2 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 0.4 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0. Load Current (mA) Figure 4.10. Typical VOL Curves, 0.9–1.8 V Rev. 1.0 Si1010/1/2/3/4 ...
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... Si1010/1/2/3/4/5 Table 4.4. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD/DC+ Monitor Thresh- old (V ) RST (all power modes except Sleep) ...
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... One-cell mode — Conditions Min Si1010/2/4 16384* Si1011/3/5 8192 512 Conditions Min 24 = 1.8–3.6 V — Conditions Min 18 = 1.8–3.6 V — Rev. 1.0 Si1010/1/2/3/4/5 Typ Max Units — 3 SYSCLKs 400 — ns 400 — — µs 10 — µs Typ Max Units — — ...
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... Si1010/1/2/3/4/5 Table 4.9. SmaRTClock Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Oscillator Frequency (LFO) Table 4.10. ADC0 Electrical Characteristics V = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) Offset Error Full Scale Error Dynamic performance (10 kHz sine-wave single-ended input below Full Scale, ...
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... V. To minimize the temperature sensor settling time, the ADC mux can be momentarily set to ground before being set to the temperature sensor output. This ensures that the temperature sensor output will settle in 3 µs or less. Si1010/1/2/3/4 +85 °C unless otherwise specified. – ...
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... Si1010/1/2/3/4/5 Table 4.12. Voltage Reference Electrical Characteristics V = 1 +85 °C unless otherwise specified. – DD Parameter Internal High Speed Reference (REFSL[1:0] = 11) Output Voltage VREF Turn-on Time Supply Current Internal Precision Reference (REFSL[1:0] = 00, REFOE = 1) Output Voltage VREF Short-Circuit Current Load Regulation Load = 0 to 200 µA to AGND VREF Turn-on Time 1 4.7 µ ...
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... IREF0DAT = 111111 — IREF0DAT = 000001 — IREF0DAT = 111111 — Low Power Mode, Sink IREF0DAT = 000001 — IREF0DAT = 111111 — High Current Mode, Sink IREF0DAT = 000001 — IREF0DAT = 111111 — Rev. 1.0 Si1010/1/2/3/4/5 Typ Max Units 6 bits — V – 0 — V – 0 — ...
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... Si1010/1/2/3/4/5 Table 4.14. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 2 1 Response Time: * Mode 2 1 Response Time: * Mode 2 1 Response Time: * Mode 2 1 Common-Mode Rejection Ratio Inverting or Non-Inverting Input Voltage Range Input Capacitance ...
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... Note: Vcm is the common-mode voltage on CP0+ and CP0–. Table 4.15. VREG0 Electrical Characteristics –40 to +85 °C unless otherwise specified 1 Parameter Input Voltage Range Bias Current Normal, idle, suspend, or stop mode Si1010/1/2/3/4/5 Conditions Min (CPnHYP/N1–0 = 00) — (CPnHYP/N1–0 = 01) — (CPnHYP/N1–0 = 10) — (CPnHYP/N1–0 = 11) — ...
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... Si1010/1/2/3/4/5 Table 4.16. DC-DC Converter (DC0) Electrical Characteristics –40 to +85 °C unless otherwise specified. VBAT = 0.9 to 1.8 V, Parameter Input Voltage Range Input Inductor Value Input Inductor Current Rating Inductor DC Resistance Input Capacitor Value Output Voltage Range Output Load Regulation Target Output = 2 Target Output = 3 Output Current ...
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... Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. txpow[2:0] = 010 (+1 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. Rev. 1.0 Si1010/1/2/3/4/5 Min Typ Max Units 1.8 3.0 3.6 V — ...
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... Si1010/1/2/3/4/5 Table 4.18. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the " ...
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... Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required it is recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for recommendations. 3. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 76. Si1010/1/2/3/4/5 1 Conditions Min 240 — ...
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... FSK 2 OOK Data Rate DR OOK Modulation Deviation Δf1 Δf2 Modulation Deviation Δf RES 2 Resolution Output Power Range— Si1010/1 Output Power Range— Si1012/3 /4/5 2 Output Steps RF_OUT 2 Output Level RF_TEMP Variation vs. Temperature Output Level ...
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... Using XTAL and board layout in reference design. Start-up time will vary with XTAL type and board layout. See “Crystal Oscillator” RES on page 270 for total load capacitance calculation RES Rev. 1.0 Si1010/1/2/3/4/5 Typ Max Units — 0.5 — °C — 5 — mV/°C — ...
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... Si1010/1/2/3/4/5 Table 4.22. Digital IO Specifications (nIRQ) Parameter Symbol Rise Time T RISE Fall Time T FALL Input Capacitance C IN Logic High Level Input V IH Voltage Logic Low Level Input V IL Voltage Input Current I IN Logic High Level Output Voltage Logic Low Level ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device. Si1010/1/2/3/4/5 –0.3, V –0. Rev ...
Page 76
... Si1010/1/2/3/4/5 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral Production Test Conditions +25 °C +3.3 VDC DD Sensitivity measured at 919 MHz TX output power measured at 915 MHz External reference signal (XOUT) = 1.0 V Production test schematic (unless noted otherwise) ...
Page 77
... SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on Si1010/1/2/3/4/5 devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation- register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate sam- ples, then place ADC0 in a low power shutdown mode without CPU intervention ...
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... Si1010/1/2/3/4/5 5.1. Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10- bit unsigned integers ...
Page 79
... SYNC bit in “SFR Definition 16.1. DC0CN: DC-DC Converter Control” on page 181 and the description of the AD0CKINV bit in “SFR Definition 16.2. DC0CF: DC-DC Converter Configuration” on page 182. This bit must be set two-cell mode for the ADC to operate. Si1010/1/2/3/4/5 Rev. 1.0 79 ...
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... Si1010/1/2/3/4/5 5.2.2. Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 4.10. The AD0TM bit in register ADC0CN con- trols the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is continuously tracked, except when a conversion is in progress ...
Page 81
... When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four SYSCLK periods. This includes external convert start signals. S yste r r ckin ckin clo cks rtin g Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 Si1010/1/2/3/4 ...
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... Si1010/1/2/3/4/5 5.2.4. Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion ...
Page 83
... ADC0L register will always read back 0x00. 5.4. 12-Bit Mode Si1010/1/2/3/4/5 devices have an enhanced SAR converter that provides 12-bit resolution while retaining the 10- and 8-bit operating modes of the other devices in the family. When configured for 12-bit conver- sions, the ADC performs four 10-bit conversions using four different reference voltages and combines the results into a single 12-bit value ...
Page 84
... Si1010/1/2/3/4/5 Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65V High-Speed VREF 8 bit 8.17 MHz Highest nominal SAR (24 clock frequency Total number of conversion clocks 11 required 1.5 us Total tracking time (min) Total time for one 2.85 us conversion ...
Page 85
... Specifies the ADC0 start of conversion source. 000: ADC0 conversion initiated on write AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 3. 1xx: ADC0 conversion initiated on rising edge of CNVSTR AD0BUSY AD0WINT R Function Rev. 1.0 Si1010/1/2/3/4 ADC0CM R ...
Page 86
... Si1010/1/2/3/4/5 SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock requirements are given in Table 4 ...
Page 87
... This bit field must be set to 000 if Burst Mode is disabled. 000: Perform and Accumulate 1 conversion. 001: Perform and Accumulate 4 conversions. 010: Perform and Accumulate 8 conversions. 011: Perform and Accumulate 16 conversions. 100: Perform and Accumulate 32 conversions. 101: Perform and Accumulate 64 conversions. All remaining bit combinations are reserved. Si1010/1/2/3/4 AD0SJST R ...
Page 88
... Si1010/1/2/3/4/5 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 AD0LPM Name R/W R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 AD0LPM ADC0 Low Power Mode Enable. Enables Low Power Mode Operation. 0: Low Power Mode disabled. ...
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... If AD0TM is set additional 3 SAR clock cycles of Track time will be inserted prior to starting the conversion. 2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first conversion should be met by the Burst Mode Power-Up Time. Si1010/1/2/3/4 ...
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... Si1010/1/2/3/4/5 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register should not be written when the SYNC bit is set to 1 ...
Page 91
... Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xC3 Bit Name 7:0 AD0GT[7:0] ADC0 Greater-Than Low Byte. Least Significant Byte of the 16-bit Greater-Than window compare register. Note: In 8-bit mode, this register should be set to 0x00. Si1010/1/2/3/4 AD0GT[15:8] R Function AD0GT[7:0] R/W ...
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... Si1010/1/2/3/4/5 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than window compare register. SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ...
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... ADC0GTH:ADC0GTL 0x0FC0 AD0WINT not affected 0x0000 0 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data 5.6.2. ADC0 Specifications See “4. Electrical Characteristics” on page 44 for a detailed listing of ADC0 specifications. Si1010/1/2/3/4/5 window comparisons for right-justified ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) ...
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... Si1010/1/2/3/4/5 5.7. ADC0 Analog Multiplexer ADC0 on Si1010/1/2/3/4/5 has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital Supply Voltage (Output of VREG0), VDD/DC+ Supply, or the positive input may be connected to GND ...
Page 95
... P0.4 00101: P0.5 00110: P0.6 00111: P0.7 01000: Reserved 01001: Reserved 01010: Reserved 01011: Reserved 01100: P1.4 01101: P1.5 01110: P1.6 01111: Reserved, Si1010/1/2/3/4 AD0MX R R/W R/W R Function 10000: 10001: 10010: 10011: 10100: 10101: 10110: 10111: 11000: 11001: 11010: 11011: ...
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... Si1010/1/2/3/4/5 5.8. Temperature Sensor An on-chip temperature sensor is included on the Si1010/1/2/3/4/5 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select the temperature sensor. The temperature sensor transfer function is shown in Figure 5 ...
Page 97
... SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14. 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V Si1010/1/2/3/4/5 40.00 0.00 60.00 20.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 80.00 -1.00 -2 ...
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... Si1010/1/2/3/4/5 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant Bits of the 10-bit temperature sensor offset measurement. ...
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... xternal V oltage R eference ircuit P 0.0 .7 .1 ecom m ended P 0.1 ypass C apacitors Figure 5.10. Voltage Reference Functional Block Diagram Si1010/1/2/3/4/5 VDD_MCU/DC+ and the external ground refer- REF ensor Internal 1.68V R eference 00 01 Internal 1. egulated D igital S upply 11 Internal 1. igh S peed R eference ...
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... Si1010/1/2/3/4/5 5.10. External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref- erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. 5.11. Internal Voltage References For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the 1 ...
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... Internal 1.68 V Precision Voltage Reference disabled and not connected to P0.0/VREF. 1: Internal 1.68 V Precision Voltage Reference enabled and connected to P0.0/VREF. 5.14. Voltage Reference Electrical Specifications See Table 4.12 on page 64 for detailed Voltage Reference Electrical Specifications REFSL TEMPE R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 REFOE R 101 ...
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... Si1010/1/2/3/4/5 6. Programmable Current Reference (IREF0) Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA steps). ...
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... CEX3 selected as fine-tuning control signal. 100: CEX4 selected as fine-tuning control signal. 101: CEX5 selected as fine tuning control signal. All Other Values: Reserved. 6.2. IREF0 Specifications See Table 4.13 on page 65 for a detailed listing of IREF0 specifications R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 PWMSS[2:0] R 103 ...
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... Si1010/1/2/3/4/5 7. Comparators Si1010/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi- cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter and the Power Management chapter for details on reset sources and low power mode wake-up sources, respectively ...
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... See the Interrupt Handler chapter for additional information. CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 + Px.x Px.x CP1 - Px.x Figure 7.2. Comparator 1 Functional Block Diagram Si1010/1/2/3/4/5 VDD CPT0MD CP1 Rising-edge + D SET D SET CLR CLR ...
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... Si1010/1/2/3/4/5 7.3. Comparator Response Time Comparator response time may be configured in software via the CPTnMD registers described on “CPT0MD: Comparator 0 Mode Selection” on page 108 and “CPT1MD: Comparator 1 Mode Selection” on page 110. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2, and Mode 3 (Lowest Power) ...
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... Positive Hysteresis = Hysteresis 1. 10: Positive Hysteresis = Hysteresis 2. 11: Positive Hysteresis = Hysteresis 3 (Maximum). 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = Hysteresis 1. 10: Negative Hysteresis = Hysteresis 2. 11: Negative Hysteresis = Hysteresis 3 (Maximum CP0FIF CP0HYP[1:0] R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 CP0HYN[1:0] R 107 ...
Page 108
... Si1010/1/2/3/4/5 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 CP0RIE Name R/W R Type 1 0 Reset SFR Page = All Pages; SFR Address = 0x9D Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Read = 0b, Write = don’t care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. ...
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... Positive Hysteresis = Hysteresis 1. 10: Positive Hysteresis = Hysteresis 2. 11: Positive Hysteresis = Hysteresis 3 (Maximum). 1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = Hysteresis 1. 10: Negative Hysteresis = Hysteresis 2. 11: Negative Hysteresis = Hysteresis 3 (Maximum CP1FIF CP1HYP[1:0] R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 CP1HYN[1:0] R 109 ...
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... Si1010/1/2/3/4/5 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection Bit 7 6 CP1RIE Name R/W R Type 1 0 Reset SFR Page = 0x0; SFR Address = 0x9C Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Read = 00b, Write = don’t care. 5 CP1RIE Comparator1 Rising-Edge Interrupt Enable. ...
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... Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on Si1010/1/2/3/4/5 devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0– are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for Comparator1 ...
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... Si1010/1/2/3/4/5 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select Bit 7 6 CMX0N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input channel for Comparator0. 0000: P0.1 0001: P0 ...
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... Function 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Rev. 1.0 Si1010/1/2/3/4 CMX1P[3:0] R/W R/W R Reserved Reserved Reserved Reserved Capacitive Touch Sense Compare VDD_MCU/DC+ divided by 2 Digital Supply Voltage Ground Reserved ...
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... Si1010/1/2/3/4/5 8. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 ...
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... Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. Si1010/1/2/3/4/5 2 2/3 3 ...
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... Si1010/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct ...
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... XCHD A, @Ri Exchange low nibble of indirect RAM with A Boolean Manipulation CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit Si1010/1/2/3/4/5 Description Rev. 1.0 Bytes Clock Cycles ...
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... Si1010/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit Move direct bit to Carry MOV bit, C ...
Page 119
... Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys- tem function. Si1010/1/2/3/4/5 Rev. 1.0 119 ...
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... Si1010/1/2/3/4/5 SFR Definition 8.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x82 Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi- rectly addressed Flash memory or XRAM ...
Page 121
... This register is the accumulator for arithmetic operations. SFR Definition 8. Register Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] B Register. This register serves as a second accumulator for certain arithmetic operations. Si1010/1/2/3/4 SP[7:0] R Function ACC[7:0] R ...
Page 122
... Si1010/1/2/3/4/5 SFR Definition 8.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition bor- row (subtraction) ...
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... Figure 9.1. Si1010/1/2/3/4/5 Memory Map 9.1. Program Memory The CIP-51 core has program memory space. The Si1010/1/2/3/4/5 devices implement 16 kB (Si1010/2/ (Si1011/3/5) of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3BFF (Si1010/2/4) or 0x1FFF (Si1011/3/5) ...
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... Data Memory The Si1010/1/2/3/4/5 device family include 768 bytes of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space of the 8051. The remainder of this memory is on-chip “external” mem- ory. The data memory map is shown in Figure 9.1 for reference. ...
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... There are 512 bytes of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN register. Si1010/1/2/3/4/5 Rev. 1.0 125 ...
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... Si1010/1/2/3/4/5 10. On-Chip XRAM The Si1010/1/2/3/4/5 MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data pointer (DPTR), or with the target address low byte and the target address high byte in the External Memory Interface Control Register (EMI0CN, shown in SFR Defi- nition 10 ...
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... RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. If EMI0CN = 0x00, addresses 0x0000 through 0x00FF will be accessed R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 PGSEL R/W R/W R 127 ...
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... SFRs used to configure and access the sub-systems unique to the Si1010/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS- 51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the Si1010/1/2/3/4/5 device family. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF ...
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... D0 PSW IREF0CF ADC0PWR CLKSEL CRC0DAT CRC0CN DPL 0(8) 1(9) 2(A) (bit addressable) Si1010/1/2/3/4/5 FLWR ADC0TK PMU0MD P0DRV P1DRV CRC0IN DC0MD CRC0FLIP DPH TOFFL 3(B) 4(C) 5(D) Rev. 1.0 EIP1 EIP2 EIE1 EIE2 SFRPAGE P2DRV CRC0AUTO CRC0CNT PCON TOFFH 6(E) 7(F) 129 ...
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... Si1010/1/2/3/4/5 SFR Definition 11.1. SFR Page: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA7 Bit Name 7:0 SFRPAGE[7:0] SFR Page. Specifies the SFR Page used when reading, writing, or modifying special function registers. Table 11.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘ ...
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... PCA0CPH0 0xFC 0x0 PCA0CPH1 0xEA 0x0 PCA0CPH2 0xEC 0x0 Si1010/1/2/3/4/5 Description CRC0 Flip CRC0 Input DC0 (DC-DC Converter) Configuration DC0 (DC-DC Converter) Control DC0 (DC-DC Converter) Mode Data Pointer High Data Pointer Low Extended Interrupt Enable 1 Extended Interrupt Enable 2 ...
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... Si1010/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page PCA0CPH3 0xEE 0x0 PCA0CPH4 0xFE 0x0 PCA0CPH5 0xD3 0x0 ...
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... VDM0CN 0xFF 0x0 XBR0 0xE1 0x0 XBR1 0xE2 0x0 XBR2 0xE3 0x0 Si1010/1/2/3/4/5 Description SPI1 Configuration SPI1 Clock Rate Control SPI1 Control SPI1 Data Timer/Counter Control Timer/Counter 0 High Timer/Counter 1 High Timer/Counter 0 Low Timer/Counter 1 Low Timer/Counter Mode Timer/Counter 2 Control Timer/Counter 2 High ...
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... Si1010/1/2/3/4/5 12. Interrupt Handler The Si1010/1/2/3/4/5 microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Refer to Table 12.1, “Interrupt Summary,” ...
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... RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Si1010/1/2/3/4/5 Rev. 1.0 135 ...
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... Si1010/1/2/3/4/5 Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 (INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B SmaRTClock Alarm 0x0043 ADC0 Window 0x004B Comparator ADC0 End of ...
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... The SFRs used to enable the interrupt sources and set their priority level are described in the following register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Si1010/1/2/3/4/5 Rev. 1.0 137 ...
Page 138
... Si1010/1/2/3/4/5 SFR Definition 12.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. ...
Page 139
... PX0 External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level PT2 PS0 PT1 R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 PX1 PT0 PX0 R/W R/W R 139 ...
Page 140
... Si1010/1/2/3/4/5 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. ...
Page 141
... PSMB0 SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level PCP0 PPCA0 PADC0 PWADC0 R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 PRTC0A PSMB0 R/W R/W R 141 ...
Page 142
... Si1010/1/2/3/4/5 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = All Pages;SFR Address = 0xE7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. 3 ESPI1 Enable EZRadioPRO Serial Interface (SPI1) Interrupt. This bit sets the masking of the SPI1 interrupts. ...
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... PWARN Supply Monitor Early Warning Interrupt Priority Control. This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt. 0: Supply Monitor Early Warning interrupt set to low priority level. 1: Supply Monitor Early Warning interrupt set to high priority level. Si1010/1/2/3/4 PSPI1 PRTC0F ...
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... Si1010/1/2/3/4/5 12.6. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “27.1. Timer 0 and Timer 1” on page 340) select level or edge sensitive ...
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... Port pin to a peripheral configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0 IN0PL R/W R Function Rev. 1.0 Si1010/1/2/3/4 IN0SL[2:0] R 145 ...
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... Si1010/1/2/3/4/5 13. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution ...
Page 147
... MOVC instruction. MOVX read instructions always target XRAM. An additional 512-byte scratchpad is available for non-volatile data storage accessible at addresses 0x0000 to 0x01FF when SFLE is set to 1. The scratchpad area cannot be used for code execution. Si1010/1/2/3/4/5 Rev. 1.0 147 ...
Page 148
... The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security features of the Si1010/1/2/3/4/5 devices. 148 8KB Flash Device ...
Page 149
... If user code writes to the Lock Byte, the Lock does not take effect until the next device reset. The scratchpad is locked when all other Flash pages are locked. The scratchpad is erased when a Flash Device Erase command is performed. Si1010/1/2/3/4/5 C2 Debug User Firmware executing from: Interface an unlocked page a locked page Permitted ...
Page 150
... The part number can be determined by reading the value of the Flash byte at address 0x3FFE. The value of the Flash byte at address 0x3FFE can be decoded as follows: 0xD4—Si1010 0xD5—Si1011 0xD6—Si1012 0xD7—Si1013 0xD8—Si1014 ...
Page 151
... To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and enabled as a reset source on Si1010/1/2/3/4/5 devices for the Flash to be successfully modified. If either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be generated when the firmware attempts to modify the Flash ...
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... Si1010/1/2/3/4/5 and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. 9. Disable interrupts prior to setting PSWE and leave them disabled until after PSWE has been reset to 0 ...
Page 153
... Minimizing Flash Read Current The Flash memory in the Si1010/1/2/3/4/5 devices is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are suggestions to minimize Flash read current. 1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the interrupt flag. ...
Page 154
... Si1010/1/2/3/4/5 SFR Definition 13.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Page =0x0; SFR Address = 0x8F Bit Name 7:3 Unused Read = 00000b, Write = don’t care. 2 SFLE Scratchpad Flash Memory Access Enable. When this bit is set, Flash MOVC reads and MOVX writes from user software are directed to the Scratchpad Flash sector ...
Page 155
... Flash, it can intentionally lock the Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1–0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. Si1010/1/2/3/4 FLKEY[7:0] R ...
Page 156
... Si1010/1/2/3/4/5 SFR Definition 13.3. FLSCL: Flash Scale Bit 7 6 BYPASS Name R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7 Reserved Always Write BYPASS Flash Read Timing One-Shot Bypass. 0: The one-shot determines the Flash read time. This setting should be used for oper- ating frequencies less than 10 MHz ...
Page 157
... Power Management Si1010/1/2/3/4/5 devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is provided in Table 14.1. Detailed descriptions of each mode can be found in the following sections ...
Page 158
... Sleep PMU0 SmaRTClock Figure 14.1. Si1010/1/2/3/4/5 Power Distribution 14.2. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data ...
Page 159
... MCU needs to be inactive for a long period of time. Note: To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be enabled by clearing the BYPASS bit (FLSCL.6). Si1010/1/2/3/4/5 Rev. 1.0 159 ...
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... Si1010/1/2/3/4/5 14.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci- sion oscillator prior to entering suspend mode. All digital logic (timers, communication peripherals, inter- rupts, CPU, etc ...
Page 161
... Port Match Event Comparator0 Rising Edge. The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply voltage of at least 1 operate properly. On ‘F912 and ‘F902 devices, the VBAT supply monitor can be Si1010/1/2/3/4/5 Rev. 1.0 161 ...
Page 162
... Si1010/1/2/3/4/5 disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor. In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep mode. In order for the MCU to respond to the pin reset event, software must not place the device back into sleep mode for a period of 15 µ ...
Page 163
... Suspend or Sleep Modes. 3. PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The wake-up source flags will read ‘0’ during the first two system clocks following the wake from Suspend mode. Si1010/1/2/3/4 ...
Page 164
... Si1010/1/2/3/4/5 SFR Definition 14.2. PMU0MD: Power Management Unit Mode Bit 7 6 Name RTCOE WAKEOE MONDIS R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xB5 Bit Name 7 Buffered SmaRTClock Output Enable. RTCOE Enables the buffered SmaRTClock oscillator output on P0.2. 0: Buffered SmaRTClock output not enabled. ...
Page 165
... Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE Idle Mode Select 14.8. Power Management Specifications See Table 4.5 on page 61 for detailed Power Management Specifications. Si1010/1/2/3/4 GF[5:0] R Write Sets the logic value. Writing 1 places the device in Stop Mode. ...
Page 166
... Si1010/1/2/3/4/5 15. Cyclic Redundancy Check Unit (CRC0) Si1010/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi- rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15 ...
Page 167
... CRC value CRC_acc = CRC_acc << Return the final remainder (CRC value) return CRC_acc; } Table 15.1 lists several input values and the associated outputs using the 16-bit Si1010/1/2/3/4/5 CRC algorithm: Table 15.1. Example 16-Bit CRC Outputs Input 0x63 0x8C 0x7D ...
Page 168
... Si1010/1/2/3/4/5 15.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be used to initialize CRC0 ...
Page 169
... An example of such an instruction is a 3-byte MOV that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction CRC0SEL CRC0INIT CRC0VAL R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 CRC0PNT[1:0] R/W R 169 ...
Page 170
... Si1010/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data being computed into the existing CRC result according to the CRC algorithm described in Section 15.1 SFR Definition 15 ...
Page 171
... Automatic CRC Calculation Starting Flash Sector. These bits specify the Flash sector to start the automatic CRC calculation. The starting address of the first Flash sector included in the automatic CRC calculation is CRC0ST x Page Size. Note: The Page Size is 512 bytes. Si1010/1/2/3/4 CRC0ST[4:0] R/W ...
Page 172
... Si1010/1/2/3/4/5 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x97 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 CRC0CNT[4:0] Automatic CRC Calculation Flash Sector Count. ...
Page 173
... Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e., the writ- ten LSB becomes the MSB. For example: If 0xC0 is written to CRC0FLIP, the data read back will be 0x03. If 0x05 is written to CRC0FLIP, the data read back will be 0xA0. Si1010/1/2/3/4/5 CRC0FLIP Write CRC0FLIP ...
Page 174
... Si1010/1/2/3/4/5 16. On-Chip DC-DC Converter (DC0) Si1014/5 devices include an on-chip dc-dc converter to allow operation from a single cell battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an input voltage range of 0.9V to 3.6 V and a programmable output voltage range of 1.8 to 3.3 V. The default output voltage is 1 ...
Page 175
... The peak inductor current is dependent on several factors including the dc load current and can be esti- mated using following equation efficiency = 0.80 inductance = 0.68 µH frequency = 2.4 MHz Si1010/1/2/3/4/5 Peak Current (mA) Peak Current (mA) Normal Power Mode Low Power Mode 100 125 250 500 ...
Page 176
... Si1010/1/2/3/4/5 16.2. High Power Applications The dc-dc converter is designed to provide the system with output power, however, it can safely provide up to 100 mW of output power without any risk of damage to the device. For high power applica- tions, the system should be carefully designed to prevent unwanted VBAT and VDD_MCU/DC+ Supply Monitor resets, which are more likely to occur when the dc-dc converter output power exceeds 65mW ...
Page 177
... The current loop including GND/VBAT–, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin should be made as short as possible to minimize capacitance. The PCB traces connecting VDD_MCU/DC+ to the output capacitor and the output capacitor to GND_MCU/DC– should be as short and as thick as possible in order to minimize parasitic inductance. Si1010/1/2/3/4/5 0.68 uH 4.7 uF VBAT GND/VBAT- DCEN ...
Page 178
... Si1010/1/2/3/4/5 16.5. Minimizing Power Supply Noise To minimize noise on the power supply lines, the GND/VBAT- and GND_MCU/DC- pins should be kept separate, as shown in Figure 16.2; GND_MCU/DC- should be connected to the pc board ground plane. The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet with respect to its own ground. However, connecting a circuit element " ...
Page 179
... The dc-dc converter would be bypassed when the battery was fresh, but as soon as the battery voltage dropped below 2.75 V, the dc-dc converter would turn on to ensure that the external chip was provided with a minimum of 2.7 V for the remainder of the battery life. Si1010/1/2/3/4/5 Rev. 1.0 179 ...
Page 180
... Si1010/1/2/3/4/5 16.10. Low Power Mode Setting the LPEN bit in the DC0CF register will enable a Low Power Mode for the dc-dc converter. In Low Power Mode, the bias currents are substantially reduced, which can lead to an efficiency improvement with light load currents (generally less than a few mA). The drawback to this mode is that the response time of the converter’ ...
Page 181
... Target output voltage is 1.9 V. 010: Target output voltage is 2.0 V. 011: Target output voltage is 2.1 V. 100: Target output voltage is 2.4 V. 101: Target output voltage is 2.7 V. 110: Target output voltage is 3.0 V. 111: Target output voltage is 3 Reserved SYNC R/W R/W R Function Rev. 1.0 Si1010/1/2/3/4 VSEL R 181 ...
Page 182
... Si1010/1/2/3/4/5 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration Bit 7 6 LPEN CLKDIV[1:0] Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0x96 Bit Name 7 LPEN Low Power Mode Enable. Enables the dc-dc low power mode which reduces bias currents, reduces peak inductor current, and increases efficiency for low load currents. Only available on ‘ ...
Page 183
... Passive Diode Mode Enable. Passive external diode mode. 0: Passive diode mode disabled. 1: Passive diode mode enabled. 16.13. DC-DC Converter Specifications See Table 4.16 on page 68 for a detailed listing of dc-dc converter specifications BYPFLG R/W R Varies Function Rev. 1.0 Si1010/1/2/3/4 BYPSEL[1:0] PASDEN R/W R 183 ...
Page 184
... Si1010/1/2/3/4/5 17. Voltage Regulator (VREG0) Si1010/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD_MCU/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in the Electrical Specifications chapter. The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in all non-Sleep power modes ...
Page 185
... Refer to Section “19. Clocking Sources” on page 194 for information on selecting and configur- ing the system clock source. The Watchdog Timer is enabled with the system clock divided its clock source (Section “28.4. Watchdog Timer Mode” on page 370 details the use of the Watchdog Timer). Program execution begins at location 0x0000. Si1010/1/2/3/4/5 Rev. 1.0 185 ...
Page 186
... The VBAT supply monitor can be disabled to save power by writing ‘1’ to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor. Note: Si1010/1/2/3 have the VBAT signal internally connected to VDD_MCU. 186 VBAT ...
Page 187
... V POR 0.6 ~0.5 See specification table for min/max voltages. RST Logic HIGH Logic LOW Figure 18.2. Power-Fail Reset Timing Diagram Si1010/1/2/3/4/5 T PORDelay Power-On Power-On Reset Reset Rev. 1.0 VBAT t T PORDelay 187 ...
Page 188
... Si1010/1/2/3/4/5 18.2. Power-Fail (VDD_MCU/DC+ Supply Monitor) Reset Si1010/1/2/3/4/5 devices have a VDD_MCU/DC+ Supply Monitor that is enabled and selected as a reset source after each power-on or power-fail reset. When enabled and selected as a reset source, any power down transition or power irregularity that causes VDD_MCU/DC+ to drop below V pin to be driven low and the CIP-51 will be held in a reset state (see Figure 18 ...
Page 189
... Enable the VDD_MCU/DC+ Supply Monitor (VDMEN bit in VDM0CN = 1). 2. Wait for the VDD_MCU/DC+ Supply Monitor to stabilize (optional). 3. Select the VDD_MCU/DC+ Supply Monitor as a reset source (PORSF bit in RSTSRC = 1). Si1010/1/2/3/4/5 Monitor as a reset source when writing DD Monitor enabled as a reset source. ...
Page 190
... Si1010/1/2/3/4/5 SFR Definition 18.1. VDM0CN: VDD_MCU/DC+ Supply Monitor Control Bit 7 6 VDMEN VDDSTAT VDDOK Name R/W R Type 1 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xFF Bit Name 7 VDMEN VDD_MCU/DC+ Supply Monitor Enable. This bit turns the VDD_MCU/DC+ supply monitor circuit on/off. The VDD_MCU/DC+ Supply Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 18 ...
Page 191
... A Program read is attempted above user code space. This occurs when user code attempts to branch address above the Lock Byte address. A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section “13.3. Security Options” on page 148). A Flash write or erase is attempted while the V Si1010/1/2/3/4/5 Monitor is disabled. DD Rev. 1.0 191 ...
Page 192
... Si1010/1/2/3/4/5 The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. 18.8. SmaRTClock (Real Time Clock) Reset The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT- Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector is enabled and the SmaRTClock clock is below approximately 20 kHz ...
Page 193
... Enable the MCD. The MCD triggers a reset if a missing clock condition is detected. 0: Disable the VDD_MCU/DC+ Supply Monitor as a reset source. 1: Enable the VDD_MCU/DC+ Supply Monitor as a reset 3 source. N/A Rev. 1.0 Si1010/1/2/3/4 PORSF PINRSF R/W R/W R Varies Varies Varies Read Set SmaRTClock alarm or oscillator fail caused the last reset ...
Page 194
... Si1010/1/2/3/4/5 19. Clocking Sources Si1010/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low power internal oscillator is automatically enabled and disabled when selected and deselected as a clock source ...
Page 195
... MHz to 24.3 MHz. 19.2. Low Power Internal Oscillator All Si1010/1/2/3/4/5 devices include a low power internal oscillator that defaults as the system clock after a system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automatically enabled when selected as the system clock and disabled when not in use. See Section “ ...
Page 196
... Si1010/1/2/3/4/5 Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference ...
Page 197
... The recommended procedure for starting the RC oscillator is as follows: 1. Configure XTAL2 for analog I/O and disable the digital output drivers. 2. Configure and enable the external oscillator. Si1010/1/2/3/4 pull-up resistor value in k capacitor value on the XTAL2 pin in pF ...
Page 198
... Si1010/1/2/3/4/5 3. Poll for XTLVLD => Switch the system clock to the external oscillator. 19.3.3. External Capacitor Mode If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode. The capacitor should be no greater than 100 pF ...
Page 199
... Special Function Registers for Selecting and Configuring the System Clock The clocking sources on Si1010/1/2/3/4/5 devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page 203 for SmaRTClock register descriptions. The system clock source for the MCU can be selected using the CLKSEL register ...
Page 200
... Si1010/1/2/3/4/5 SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 CLKRDY CLKDIV[2:0] Name R R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA9 Bit Name 7 CLKRDY System Clock Divider Clock Ready Flag. 0: The selected clock divide setting has not been applied to the system clock. ...