ATMEGA1284PR212-AU Atmel, ATMEGA1284PR212-AU Datasheet - Page 212
ATMEGA1284PR212-AU
Manufacturer Part Number
ATMEGA1284PR212-AU
Description
BUNDLE ATMEGA1284P/RF212 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284PR212-AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (7Mb)
8059D–AVR–11/09
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 19-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
Synchronized
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
Arbitration, SDA
Master A Loses
ATmega1284P
A
SDA
212
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