ATZB-A24-UFL Atmel, ATZB-A24-UFL Datasheet - Page 15

• Manufacturer Part Number: ATZB-A24-UFL
• Description: KIT MOD 802.15.4/ZIGB 2.4GHZ W/U
• Manufacturer: Atmel

Specifications of ATZB-A24-UFL

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 20dBm
• Sensitivity: -104dBm
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Receiving: 23mA
• Current - Transmitting: 50mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
• Antenna Connector: U.FL
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ZigBit™ 2.4 GHz Amplified Wireless Modules
Table 3-6. Pin descriptions
Notes:
44,45,51,52,
Connector
53,56,57
46,47
48,50
54,55
Pin
35
36
37
38
39
40
41
42
43
49
1. The UART_TXD pin is intended for input (i.e. its designation as "TXD" implies some complex system
2. Most of pins can be configured for general purpose I/O or for some alternate functions as described in
3. GPIO pins can be programmed either for output, or for input with/without pull-up resistors. Output pin
4. All digital pins are provided with protection diodes to D_VCC and DGND
5. It is strongly recommended to avoid assigning an alternate function for OSC32K_OUT pin because it is
6. Normally, JTAG_TMS, JTAG_TDI, JTAG_TDO, JTAG_TCK pins are used for on-chip debugging and
7. The following pins can be configured with the BitCloud software to be general-purpose I/O lines:
8. With BitCloud, CTS pin can be configured to indicate sleep/active condition of the module thus provid-
containing ZigBit Amp as its RF terminal unit), while UART_RXD pin, vice versa is for output.
details in the ATmega1281V Datasheet [3].
drivers are strong enough to drive LED displays directly (refer to figures on pages 387-388, [3]).
used by BitCloud. However, this signal can be used if another peripheral or host processor requires
32.768 kHz clock, otherwise this pin can be disconnected.
flash burning. They can be used for A/D conversion if JTAGEN fuse is disabled.
GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO_1WR, I2C_CLK, I2C_DATA,
UART_TXD, UART_RXD, UART_RTS, UART_CTS, ADC_INPUT_3, ADC_INPUT_2, ADC_INPUT_1,
BAT, UART_DTR, USART0_RXD, USART0_TXD, USART0_EXTCLK, IRQ_7, IRQ_6. Additionally, four
JTAG lines can be programmed with software as GPIO as well, but this requires changing the fuse bits
and will disable JTAG debugging.
ing mechanism for power management of host processor. If this function is necessary, connection of
this pin to external pull-down resistor is recommended to prevent the undesirable transients during
module reset process.
USART0_EXTCLK
USART0_RXD
USART0_TXD
GPIO9/1_WR
UART_DTR
Pin Name
RF GND
RFP_IO
GPIO8
AGND
IRQ_7
IRQ_6
DGND
VRR
VTT
DTR input (Data Terminal Ready) for UART.
Digital Input Interrupt request 7
Digital Input Interrupt request 6
General Purpose digital input/output 9 /
USART/SPI External Clock
General Purpose Digital Input/Output
USART /SPI Transmit pin
USART/SPI Receive pin
Differential RF Input/Output
Transmitter supply voltage
RF Analog Ground
Receiver supply voltage
1-wire interface
Active low
Analog ground
Digital ground
Description
(2)(3)(4)(7)
(2)(3)(4)(7)
(2)(3)(4)(7)
(2)(3)(4)(7)(11)
(2)(3)(4)(7)
(2)(3)(4)(7)
(9)
(2)(3)(4)(7)
(2)(3)(4)(7)
(9)
(10)
8228B–MCU Wireless–06/09
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
Specifications
State after
Power on
Default
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
3-12