ATZB-24-A2 Atmel, ATZB-24-A2 Datasheet - Page 96

• Manufacturer Part Number: ATZB-24-A2
• Description: KIT MOD 802.15.4/ZIGB 2.4GHZ ANT
• Manufacturer: Atmel

Specifications of ATZB-24-A2

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Tool Type: Wireless Development Kit
• Core Architecture: AVR
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Description/function: ZigBit 2.4 GHz Dual Chip Antenna
• Wireless Frequency: 2.4 GHz
• Interface Type: UART, I2C, SPI
• Operating Voltage: 1.8 V to 3.6 V
• Output Power: 3 dBm
• Antenna: Chip Antenna
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8069Q–AVR–12/10
11. Sampled BOD in Active mode will cause noise when bandgap is used as reference
12. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
13.
14. EEPROM page buffer always written when NVM DATA0 is written
15. Pending full asynchronous pin change interrupts will not wake the device
16. Pin configuration does not affect Analog Comparator output
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC or the Analog Comparator, the
BOD must not be set in sampled mode.
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
XMEGA A4
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